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mo9652962-ai

circuit-agent

by mo9652962-ai

run_pcb_drc

Read-onlyIdempotent

Execute rigorous physical Design Rule Check (DRC) on a routed PCB and return a scored violation report. Verifies what the router cannot: true copper-to-copper clearance between different nets (segment-to-segment geometry, not grid cells)…

Instructions

Execute rigorous physical Design Rule Check (DRC) on a routed PCB and return a scored violation report. Verifies what the router cannot: true copper-to-copper clearance between different nets (segment-to-segment geometry, not grid cells), acid traps and sub-90-degree etching crevices (IPC-2221B 10.1.2), trace width vs process capability, board-edge and mounting-hole keepout intrusion, RF antenna keepout, and high-speed differential pair skew (IPC-2141A 3.4). Returns severity-tagged violations with measured vs required values plus a 0-100 score; passed is false when any blocking error remains.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
modulesYesComponent modules dict (from synthesize_circuit output).
netlistYesNetlist dict with 'connections' (from synthesize_circuit output).
ses_textNoSpecctra SES session text to check. When omitted the board is routed first with the default exact engine, so the report describes what would actually be fabricated.
board_width_mmNoPCB width in mm (default: 70.0).
board_height_mmNoPCB height in mm (default: 50.0).
check_acid_trapsNoWhether to check acute-angle etching traps and 90-degree high-speed corners (default: true).
max_diff_skew_mmNoMaximum allowed USB differential pair length mismatch in mm (default: 1.250).
min_clearance_mmNoMinimum copper-to-copper clearance in mm (default: 0.100 / 4mil).
edge_clearance_mmNoMinimum copper-to-board-edge setback in mm (default: 0.800).
min_trace_width_mmNoMinimum manufacturable trace width in mm (default: 0.127 / 5mil).

Schema Changelog

Changes observed during successful MCP inspections.

  1. Addedv0.16.0

TDQS

Score is being calculated.

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