render_circuit_topology
Generate an ASCII schematic of power domains, buses, and connected subsystems from a hardware netlist to visualize circuit architecture and verify connectivity.
Instructions
Render a clean, structured ASCII architectural diagram of power domains, buses, and connected subsystems.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"netlist": "<netlist>"
},
"name": "render_circuit_topology"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| netlist | Yes | Hardware netlist dictionary or synthesis result. |