audit_fab_capabilities
Audits PCB design rules against fab house capabilities to prevent CAM engineering query rejections. Checks trace width, clearance, via drill, annular ring, aspect ratio, and slot width for JLCPCB, PCBWay, OSH Park.
Instructions
Audit PCB layout physical design rules against real-world fab house capabilities (JLCPCB standard/advanced, PCBWay, OSH Park): verifies min trace width, min clearance, min via drill, annular ring, aspect ratio, and slot width against published fab process limits to prevent CAM engineering query (EQ) rejections.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| fab_id | No | Fab house identifier: 'jlcpcb_standard' (default), 'jlcpcb_advanced', 'pcbway_standard', 'oshpark_standard'. | jlcpcb_standard |
| min_via_pad_mm | No | Smallest via outer pad diameter in mm (default: 0.450). | |
| min_via_drill_mm | No | Smallest via drill diameter in mm (default: 0.200). | |
| min_slot_width_mm | No | Smallest mechanical milled slot width in mm (default: 0.800). | |
| board_thickness_mm | No | Nominal PCB thickness in mm (default: 1.600). | |
| min_trace_width_mm | No | Smallest conductor trace width in mm (default: 0.127). | |
| min_trace_clearance_mm | No | Smallest conductor-to-conductor gap in mm (default: 0.127). |