Synthesize a deterministic hardware netlist and component modules from a natural language prompt. Supported MCUs: STM32F103, ESP32-C3, ESP32-S3, RP2040, STC89C52, CH32V003, STM32G030, ATmega328P. Peripherals: Type-C, LDO, Crystal, Buttons, LEDs, Buzzer, I2C, RS485, CAN, TP4056 Battery, AHT20 Temp/Humidity Sensor, MPU6050 6-Axis Motion Sensor.

List all registered MCU chips and third-party pinout allocation rules (e.g. CH32V003, STM32G030, ATmega328P).

Register or dynamically override a third-party microcontroller pinout and peripheral multiplexing rule.

Query live LCSC / JLCPCB component inventory, stock, package, and pricing with zero API keys required. Features 24-hour disk cache and exponential backoff.

List all 10 pre-validated CircuitBlocks available in the hardware DSL catalog.

Run deterministic Electrical Rules Check (ERC) on a netlist: floating nets, missing GND, unknown designators, missing power domain, missing decoupling. Every finding carries severity + source; blocking/error issues gate BOM/CPL delivery.

Validate a hardware netlist dictionary against the formal CircuitAgent JSON Schema specification.

Calculate characteristic impedance (Z0) or differential impedance (Zdiff) for PCB microstrip traces using IPC-2141 / Wheeler equations. Solves exact trace width W and spacing S for target impedance (e.g. 50Ω RF, 90Ω USB, 120Ω RS485/CAN).

Calculate PCBA component cost breakdown and estimate JLCPCB SMT manufacturing surcharges. Identifies Basic library parts (¥0 feeder fee) vs Extended library parts (+¥20/type feeder fee) and suggests cost optimizations.

Calculate conductor current-carrying capacity or solve required PCB trace width according to IPC-2152 standards for given copper weight (oz), temperature rise (ΔT °C), and layer position.

Execute an enterprise-grade DFX (DFM/DFA/DFT/DFC/EMC) compliance audit on a schematic netlist. Verifies optical fiducials (MARK points), ICT testpoint coverage on power/debug rails, IEC 61000-4-2 TVS surge protection on exposed ports (USB, RS485, CAN), reverse polarity protection, and SMT costs.

Export standard KiCad S-Expression netlist (.net) compatible with KiCad 6/7/8/9/10 Pcbnew.

Generate production-ready JLCPCB SMT BOM CSV with part grouping, designator aggregation, and Basic/Extended classification.

Generate the JLCPCB SMT pick-and-place (CPL/pos) file with designator, centre X/Y in mm, layer and rotation. Required alongside the BOM for assembly: a part in the BOM but absent here is purchased and never soldered.

Solve discrete parametric circuit equations: optimal E96 resistor dividers, LDO thermal dissipation, I2C bus pullups, or RC filters.

Render a clean, structured ASCII architectural diagram of power domains, buses, and connected subsystems.

Analyze system-level power distribution architecture, load current budgets (typical & peak mA), regulator dropout headroom, and LDO thermal dissipation / junction temperature estimates.

Calculate minimum electrical clearance (conductor spacing) according to IPC-2221B Table 6-1 based on peak voltage and conductor classification (B1 internal, B2 external uncoated, B4 coated, A6 leads).

Generate universal Specctra DSN (v15.0) auto-router interchange file for automated PCB track routing in Freerouting, Cadence Specctra, Altium, or KiCad. Includes heuristic component auto-placement.

Execute automated native PCB layout and multi-layer track routing on circuit specifications. Generates standard Specctra SES (Session) routing data and comprehensive physical metrics (completion rate, total track length, via count, layer utilization) with zero JVM dependencies.

Export modern KiCad 8/9 S-Expression schematic file (.kicad_sch) directly viewable and editable in KiCad Eeschema with sheet layout, component symbols, pin references, and LCSC attributes.

Audit BOM component multi-sourcing resilience (ISO 9001 supply chain audit), identifying single-source bottlenecks and mapping pin-compatible second-source drop-in replacements with LCSC cross-references.

Solve high-speed differential pair intra-pair propagation delay skew (USB 2.0 HS ≤10ps, Ethernet ≤25ps, CAN-FD ≤50ps) and calculate required serpentine length matching tuning bumps count and geometry.

Generate universal IPC-D-356A ASCII bare-board electrical test netlist file for flying probe testers (AEMG, ATG, MicroCraft) and bed-of-nails PCB fabrication test fixtures.

Generate native fabrication-ready Gerber RS-274X + Excellon bundle (Edge_Cuts .gm1, Top/Bottom Copper .gtl/.gbl, Top/Bottom Mask .gts/.gbs, Top Silkscreen .gto, drill .drl) directly from placed modules and netlist, eliminating GUI EDA dependency. Copper layers carry real footprint pads and the autorouter's actual track geometry.

Lookup standard industrial 4-layer (JLC04161H) and 6-layer (JLC06161H) PCB stackup matrices and solve target controlled impedance trace widths (50Ω RF, 90Ω USB, 100Ω Ethernet, 120Ω CAN/485, IPC-2141A).

Generate production IPC-NC-349 Excellon CNC drill file (.drl) with metric tool headers (T01C... T02C...), completing the 5-layer PCB manufacturing bundle for automated CNC drilling machines.

Generate a lightweight self-contained single-file Interactive HTML BOM (iBOM, InteractiveHtmlBom-compatible) with interactive component grouping table, vector SVG board map, and bidirectional hover/click inspection.

Optimize SMT pick-and-place feeder slot allocation (8mm/12mm/16mm/24mm) and nozzle tooling selection (502/503/504/505/506) according to EIA-481 carrier tape standard and OpenPnP/Juki machine matrices.

Generate production OpenPnP and industrial SMT pick-and-place board job CSV (part, designator, X/Y coords, rotation, nozzle ID, feeder slot assignment) for automated robotic assembly.

Calculate mathematically compliant surface mount land pattern geometry (pad width X, pad length Y, pad center distance C, and courtyard boundary bounds) based on IPC-7351B standards across Density Levels A (Most), B (Nominal), and C (Least).

Calculate SMT automated assembly panel frame with breakaway process rails, conveyor clamp clearances, SMEMA tooling holes (NPTH Φ3.2mm), optical fiducials (Φ1.0mm/Φ3.0mm mask), and de-paneling features (V-Cut score lines or perforated mouse-bites) per IPC-2221B Section 8.4 and IPC-SMEMA-9851.

Analyze PCB netlist testability, allocate automated bed-of-nails In-Circuit Test (ICT) testpoints (B.Cu Φ1.0mm), assign probe tip types (crown, spear, serrated), and verify fault coverage percentage per IPC-9252 & IPC-2221B.

Calculate BGA diagonal dogbone via fanout geometry, escape channel trace widths and clearances, and minimum signal layer requirements per IPC-7095 Section 5.2.

Calculate tangent teardrop fillets for PCB vias, circular pads, and testpoints to prevent drill breakout, eliminate mechanical/thermal crack stress, and comply with IPC-2221B Section 9.1.5 and IPC-A-600J Class 3.

Calculate layer copper density balance between top and bottom layers, assess reflow thermal bow/twist warpage risk (IPC-TM-650 2.4.22 <= 0.75%), and generate non-functional dummy copper thieving dot/grid patterns per IPC-2221B Section 10.1.1.

Calculate thermal via matrix array under QFN/power exposed pads (IPC-7093 Section 7.2) or RF ground shielding fence via arrays (IPC-2141A <= lambda/10 pitch) with thermal resistance reduction metrics.

Calculate high-speed differential pair serpentine delay tuning meander geometry, ensuring self-coupling suppression (S >= 3W, H >= 3W) and generating vertex paths per IPC-2141A Section 5.3.

Evaluate SMT stencil aperture area ratio (>= 0.66 laser-cut) and aspect ratio (>= 1.5) compliance per IPC-7525 Stencil Design Guidelines, identifying paste-release-deficient apertures.

Generate asymmetric 3-point global optical fiducial layout (L-shape, 180° rotation unambiguous) and 2-point local fiducials for fine-pitch components per IPC-2221B Section 12 and JEDEC J-STD-020.

Select IPC-4761 via protection types (Type I ~ VII) per via assembly context: Type VII filled-and-capped (VIPPO) mandatory for BGA via-in-pad, Type V fill for thermal pads, Type IV tent+plug for BGA channels, Type II tent for free vias.

Assess per-aperture deposited solder paste volume against target joint volume per IPC-7525A transfer analysis (accepted ratio window 1.0 ~ 2.5), flagging starved joints and excessive paste defects.

Export a simplified IPC-2581B single-file intelligent fabrication data package (XML) — stackup, BOM, placed components, nets with pin membership, and board profile — replacing the legacy Gerber+Excellon+TXT handoff bundle accepted by Siemens X / Altium / Zuken / EMS houses.

Generate a scaled PCBA assembly drawing SVG per ASME Y14.5 and IPC-2221B Section 11: body outlines with refDes labels, polarity marks (pin-1 dots, cathode bars, plus frames), mirrored bottom view, and an ASME Y14.100 title block with revision and check signature.

Engineering Change Order (ECO) netlist diff: compare two netlist revisions and report added/removed components, value/package changes, added/removed nets, pin membership moves, total change count, and ECO severity (NONE / MINOR / MAJOR) for PLM change management.

Generate a mixed-assembly process route plan: classify each component into SMD reflow / THT wave / THT manual / mechanical stages per IPC-A-610G Section 7, output the 10-stage EMS routing (SPI -> reflow -> AOI -> THT insert -> wave -> manual -> ICT -> FCT -> coating -> packing).

Enumerate panel grid combinations (grid_x x grid_y, rail sides, V-cut vs mouse-bites), filter options exceeding the max panel size (default 300x300mm fab limit), and rank feasible layouts by material utilization percentage.

Estimate PCB fabrication cost from fab-house published tiered pricing: layers (2/4/6), quantity tiers (5/10/30/100), area surcharge beyond 100x100mm, solder mask color, surface finish (HASL/ENIG/OSP), board thickness, and lead time (normal/48h/24h). Estimate only.

Analyze SMT pick-and-place nozzle collision clearance between tall (H >= 4.0mm) and low components, evaluate nozzle keepout envelopes (min 2.0mm horizontal gap), and generate layered placement priority sequences (lowest to tallest) per IPC-SM-782 and OpenPnP guidelines.

Evaluate high-voltage electrical creepage compliance per IPC-2221B Table 6-1 and IEC 62368-1, and plan an air isolation milled slot (slot width, length, endpoints, and expanded effective creepage path) between high-voltage and low-voltage conductors when surface distance is insufficient.

Analyze PCB characteristic impedance manufacturing tolerance window and sensitivities per IPC-2141A and Polar SI9000 models: evaluates dielectric height (+-10%), trace width (+-10%), copper thickness (+-15%), and Er (+-5%) cumulative variations, calculating Zmin, Zmax, dZ/dW, dZ/dH, and yield within +-10% target.

Evaluate substrate Comparative Tracking Index (CTI) Material Group (Group I >= 600V to Group IIIb) and required safety creepage under Pollution Degrees 1/2/3 and Basic/Reinforced insulation per IEC 62368-1 Table 25 and IPC-2221B, calculating safety margins and recommending high-CTI laminates.

Audit bottom-side SMD component wave soldering orientation angles and hydrodynamic shadowing per IPC-7351B and SMTA guidelines: chip passives (0603/0805) perpendicular to flow to prevent tombstoning, SOIC ICs parallel to flow to prevent solder bridging, and 3xH shadow keepout zones behind tall components.

Evaluate automotive and industrial solderless press-fit compliant pin (eye-of-the-needle) finished hole diameter tolerances (standard 0.94mm ~ 1.09mm) and copper barrel plating thickness (>= 25μm) per IPC-9797 and IEC 60352-5, estimating insertion and retention forces to prevent inner-layer tear or vibration disconnects.

Audit PCB layout physical design rules against real-world fab house capabilities (JLCPCB standard/advanced, PCBWay, OSH Park): verifies min trace width, min clearance, min via drill, annular ring, aspect ratio, and slot width against published fab process limits to prevent CAM engineering query (EQ) rejections.

One-call industrial release gate: synthesizes from a prompt, places, autoroutes, exports the full 9-layer fab bundle (copper, mask, silk, stencil, drill, BOM, CPL), then runs the manufacturing validator including solder-mask dam width. Returns a single production_ready verdict plus the blocking defects, so a CI job or a contract manufacturer can decide go/no-go without reading five separate reports.

Headless manufacturing package validator for automated CI/CD and developer hand-off: checks completeness and non-emptiness of 5-layer Gerbers, Excellon drill, BOM, and CPL, verifies component refDes consistency, and calculates SHA-256 cryptographic tamper-proof ledger.

Audit PCB physical and metallurgical design parameters against IPC-6012E and IPC-A-600J Class 1/2/3 acceptance criteria: evaluates external/internal annular rings, zero-breakout constraints for Class 3, PTH copper barrel plating thickness (avg >= 25μm for Class 3), etch conductor width reduction, and solder mask dam widths.

Optimize SMT pick-and-place feeder trolley allocation (Panasonic NPM / Fuji NXT / ASM SIPLACE standard 80-slot cart): applies Group Technology (GT) to pin permanent common passive reels (100nF, 10k), places high-frequency reels near the gantry center to minimize travel time, and forecasts reel run-out exhaustion points per batch size per IPC-9851.

Calculate DC IR-drop, Joule heating dissipation, and localized bottleneck current density in polygon copper pours and power busbars per IPC-2152 Section 5.0 and IEC 60092-352, verifying current density <= 35.0 A/mm² to prevent copper foil delamination or blistering under heavy loads.

Audit SMD plastic packages (BGA, QFN, CSP, TQFP) for moisture sensitivity level (MSL 1 to 6) and open-bag shop floor life per JEDEC J-STD-033D and IPC-M-109, flagging expired components and generating recommended dehumidification baking schedules (e.g. 125°C for 24h or 40°C for 192h) to prevent 260°C reflow popcorning defects.

Effective capacitance of a Class II MLCC at real operating conditions — the marked value is not the value in circuit. Multiplies the four loss mechanisms that compound: DC bias (the dominant one, typically 35-65% loss at rated voltage and worse in small cases), AC signal level, temperature coefficient, and logarithmic dielectric ageing, then applies the part tolerance. Returns the full factor stack so you can see which mechanism hurt most. Class I (C0G/NP0) parts correctly short-circuit to tolerance-only. Pass measured_retention_at_bias from a datasheet curve (Murata SimSurfing, TDK SEAT) to replace the band estimate and get confidence='measured'.

Size an MLCC reservoir bank for a brown-out ride-through window in EFFECTIVE farads, then report the marked value you must actually buy. Solves C = I·t/ΔV for the required effective capacitance and divides by the retention at the worst-case bias in the window, because sizing from the marked value is how a design that 'passes' delivers 0.85 ms of hold-up when the spec asked for 20 ms. Reports the achieved hold time, the shortfall, and the required marked capacitance.

RC filter cutoff computed from the capacitance the part actually has, not the marked value. A 1 kHz filter built with a 10 µF X5R part that delivers 4 µF under bias cuts at 2.5 kHz — the nominal calculation is not wrong, it answers a different question. Returns nominal vs actual cutoff, the drift percentage, and the retention that caused it.

Tolerance band of a resistor divider — nominal is not a specification. Reports BOTH the exact worst case (corner enumeration, valid because the transfer function is monotonic in each resistor) and the realistic statistical band (first-order sensitivity propagation, NOT naive RSS of percentage tolerances — the output is a quotient of random variables, so RSS-ing the percentages directly is invalid; TI SNVA112 states this explicitly). Includes TCR, sqrt-of-time life drift, supply tolerance, and matched-pair ratio tolerance, and names which resistor dominates the error budget so you fix the right part.

End-of-life resistance band for one resistor from the four-term error model: value tolerance, temperature coefficient, life drift, and (for matched networks) ratio tolerance. Reports both the RSS band and the linear worst-case band, and names the dominant term — because buying a ±0.1% thick-film part to fix an accuracy problem does nothing when its 200 ppm/°C TCR already contributes 1.2% over a 60 °C excursion. Life drift scales with sqrt of the time ratio (random walk, not a ramp).

Exact R1/R2 feedback divider pair for a regulator or comparator target, plus the static error the E96 snap adds. The ideal pair almost never exists in E96, and that snap error is a wrongness, not a tolerance: it is identical on every board and must be budgeted separately from the tolerance band.

Calculate high-frequency skin effect depth, Hammerstad surface roughness correction factor (Ksr), and conductor attenuation per IPC-4562B and IPC-2141A for 1GHz to 50GHz signals (PCIe 5.0/6.0, USB4, 112G PAM4), recommending standard ED, VLP, or HVLP/RTF copper foil profiles to recover high-speed signal integrity eye margins.

Plan IPC-9252B bare-board electrical test recipes (flying probe or bed-of-nails universal grid): establishes continuity thresholds (signal <= 10Ω, power <= 2Ω) and isolation test voltages (Class 1: 50V, Class 2: 100V, Class 3: 250V), automatically derating test voltages to 100V on fine-pitch (<0.100mm) or sensitive RF nets to prevent dielectric breakdown arc-over damage.

Execute rigorous physical Design Rule Check (DRC) on a routed PCB and return a scored violation report. Verifies what the router cannot: true copper-to-copper clearance between different nets (segment-to-segment geometry, not grid cells), acid traps and sub-90-degree etching crevices (IPC-2221B 10.1.2), trace width vs process capability, board-edge and mounting-hole keepout intrusion, RF antenna keepout, and high-speed differential pair skew (IPC-2141A 3.4). Returns severity-tagged violations with measured vs required values plus a 0-100 score; passed is false when any blocking error remains.

Post-clean ionic contamination (ROSE) and ion chromatography compliance analyzer per IPC-CH-65 and IPC-TM-650 2.3.25/2.3.28: compares NaCl-equivalent loading against class limits (1.56 μg/cm² standard, 1.20 Class 3), flags per-species halide carryover (chloride 0.70, bromide 0.54 μg/cm²), and scores dendrite/CAF risk from bias voltage and conductor pitch.

ENIG/ENEPIG plating thickness and black-pad (interfacial nickel corrosion) risk auditor per IPC-4552A and IPC-4556: verifies gold 0.050.20 μm, nickel 3.06.0 μm, phosphorus 710 wt%, and ENEPIG palladium 0.100.30 μm windows; scores galvanic black-pad susceptibility from phosphorus content, gold over-deposition, rework cycles, and process type, and flags gold >0.25 μm solder embrittlement.