sch_get_constraint_groups
Enumerate constraint groups on the active schematic to audit FPGA pin and timing constraints that do not appear in the regular PCB design-rule list.
Instructions
Enumerate IDocument.DM_ConstraintGroups on the active schematic.
Constraint groups are FPGA-style pin/timing constraints attached to a document. Each group has a target kind and id, plus a list of IConstraint entries with a kind/data payload. Useful for auditing FPGA pin assignments and timing constraints that don't show up in the regular PCB design-rule list.
Returns: Dict with groups (list of {target_kind, target_id, constraint_count, constraints[{kind, data}, ...]}) and count.
Input Schema
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Output Schema
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