pcb_place_stitching_vias
Places a grid of stitching vias on a specified net within a rectangle to create low-inductance return paths; defaults to a dry run and skips conflicting primitives.
Instructions
Place a grid of stitching vias on a named net within a rectangle.
Standard RF / EMC tool: place GND stitch vias around high-speed traces so the return current has a low-inductance path between reference planes. Also used near connectors / clock generators / EMI-sensitive areas.
Algorithm: walk a regular grid inside the rectangle; for each
gridpoint, spatial-iterate within via_size_mils/2 + clearance_mils. Skip the gridpoint if any non-same-net
primitive (pad / via / track / arc) is in range. Otherwise
create a top→bottom through-via on the target net.
The default is dry-run because mutating a board with N×M
new vias is risky. Confirm the placed / skipped count
looks right, then call again with dry_run=False.
Args: net: Target net (must already exist on the board). x1_mils, y1_mils, x2_mils, y2_mils: Inclusive rectangle where the grid is placed. PCB origin is bottom-left by Altium convention. spacing_mils: Grid spacing (default 50). For GND stitching near a high-speed bus, /4 of the wavelength of the highest harmonic is a common rule of thumb. via_size_mils: Via pad diameter (default 30). via_hole_mils: Via drill diameter (default 14). clearance_mils: Min gap to any non-same-net existing primitive (default 10). dry_run: When True (default), only count would-be placements without mutating the board.
Returns:
Dict with {net, dry_run, placed, skipped, spacing_mils, clearance_mils}.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| net | Yes | ||
| dry_run | No | ||
| x1_mils | Yes | ||
| x2_mils | Yes | ||
| y1_mils | Yes | ||
| y2_mils | Yes | ||
| spacing_mils | No | ||
| via_hole_mils | No | ||
| via_size_mils | No | ||
| clearance_mils | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||