design_synthesize_rules
Synthesize PCB design rules and stackup operations from a validated fab profile and design plan, tracing every width and impedance value to profile fields or IPC calculators.
Instructions
Synthesize PCB design rules + stackup ops from a fab profile.
Stage 8 of the autonomous flow (rules & stackup,
reference/autonomy-roadmap.md): turn the validated fab profile, the
plan's net classes, and a few board-level targets into the concrete
pcb_create_design_rule and pcb_modify_layer parameter dicts,
dispatched verbatim after pcb_create_net_class creates classes
named after the synthesized groups. Every number traces to a
profile field or a verified calculator (IPC-2221 width inverse,
IPC-2141 impedance inverse); a rule whose inputs are missing is
skipped with a note, never guessed. Pure Python, no Altium.
Args:
profile: FabProfile as a dict (see design_load_fab_profile).
plan_json: Optional DesignPlan (JSON string or dict). When given
and net_class_map is not, net classes are derived from
the plan (flags + net roles, naming-agnostic).
net_class_map: Optional explicit {net_name: class} map;
takes precedence over plan_json derivation.
options: Optional synthesis targets: stackup (name, default
first), class_current_a ({class: amps} -> per-class
width rules), delta_t_c, track_margin, layer,
copper_oz, geometry, diff_pair_target_ohms
(required for differential rules),
diff_pair_spacing_mils.
Returns:
{"ok": True, "rules": [...], "stackup_ops": [...], "notes": [...], "stackup": name|None, "net_classes": {...}}
-- rule values are INTEGER MILS -- or
{"ok": False, "reason": "..."}.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| options | No | ||
| profile | Yes | ||
| plan_json | No | ||
| net_class_map | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||