design_audit_schematic
Audit the active schematic for component overlaps, wire crossings, and stacked ports, returning geometry so layout issues can be fixed before ERC validation.
Instructions
Structured visual/layout audit of the active schematic.
Call AFTER design_execute_plan and BEFORE design_validate
so layout problems are fixed first; ERC violations downstream are
less noisy. Detects three classes of issue, each with enough
geometry for the planner to compute a corrective move:
overlaps - pairs of components whose bboxes intersect
wire_crossings - wire segments that cross a component body (excluding pin-to-pin connections)
stacked_ports - 3+ power/ground glyphs of the same net huddled inside
cluster_radius_mils
Args: project_path: Optional .PrjPcb path. None uses the focused project. cluster_radius_mils: Radius for stacked-port clustering. Default 600 mils.
Returns:
SchematicAuditReport dict: {ok, project_path, overlaps[], wire_crossings[], stacked_ports[], notes[]}.
ok=True iff every list is empty.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| project_path | No | ||
| cluster_radius_mils | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||