design_validate
Runs ERC and connectivity checks on a schematic project, bundling errors, warnings, and unconnected pins into a structured report so design issues can be found and fixed before layout.
Instructions
ERC + connectivity sanity report on the focused project.
Runs run_erc, project.get_messages, and get_unconnected_pins, then bundles the output into a structured ValidationReport that the planner can read and respond to. Schematic-only in this slice, PCB validation is a separate later slice.
Args: project_path: Optional absolute path to a .PrjPcb. If omitted, uses the focused project.
Returns:
ValidationReport dict: {passed, project_path, errors, warnings, notes} where each error/warning is an Issue with
{category, severity, text, refdes, pin, net, sheet}.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| project_path | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||