design_solve_netlist_file
Rebuilds a single .SchDoc netlist from schematic geometry without Altium, then checks connectivity for floating pins and rail shorts. Use as an offline fallback when live Altium is unavailable.
Instructions
Reconstruct a .SchDoc's netlist geometrically: OFF by default.
Offline FALLBACK, same opt-in as design_review_file. Parses the
file (no Altium, no license) and rebuilds the compiled netlist from
geometry (pins, wires, power ports, junctions, and by-name net
labels), then runs connectivity ERC (single_pin_net floating
pins, net_short rail shorts).
Prefer the live-Altium path (proj_get_nets / proj_run_erc)
whenever a session is available: Altium's own compiler is ground
truth. Use this only when Altium can't be opened.
Validated envelope: wire + power port + junction + net-label
connectivity (live Altium 24/24; pipeline buck 7/7). It faithfully
reports a net the schematic left floating; cross-sheet connectors are
out of scope. A single sheet only (a .SchDoc), not a project.
Enable with EDA_AGENT_HEADLESS_REVIEW=1.
Returns {file, net_count, nets, pin_count, findings}: or
{"error": ...} if disabled or unreadable.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||