design_connect_bus
Wires a parallel bus across multiple parts in one call, joining the i-th pin of each endpoint into one net per bit to keep wide interfaces aligned without manual net-by-net wiring.
Instructions
Wire a parallel bus across two+ parts in one call.
A wide interface -- an 8-bit data bus between an MCU and a display, an address bus to a memory -- is otherwise N near-identical net objects where bit i of one side is easily misaligned with bit i+1 of the other. This joins the i-th pin of every endpoint into one net per bit, so alignment is structural and the whole bus is one call. It creates NO parts: the endpoints reference parts already in the plan. The nets share one part-set -- the signature the pipeline uses to DRAW a >=4-bit bus as a bus glyph automatically.
Args:
plan_json: the DesignPlan as a JSON string or dict.
endpoints: one dict per part on the bus, {"refdes": str, "pins": [pin, ...]}. Every endpoint must list the same
number of pins (the bus width); bit i joins pins[i] of
each endpoint.
net_names: explicit name per bit (length must equal the width);
omitted -> f"{net_prefix}{start_index+i}" (D0, D1, ...).
net_prefix: prefix for auto-named bits.
start_index: first bit number for auto-naming.
Returns:
{ok, plan, added: {nets, extended_nets}, notes, validation}
-- same shape as design_add_circuit_block. ok is False
on a bad endpoint / width mismatch / schema error.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| endpoints | Yes | ||
| net_names | No | ||
| plan_json | Yes | ||
| net_prefix | No | D | |
| start_index | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||