synthesize
Synthesize HDL source code (Verilog, SystemVerilog, VHDL) using Yosys or LiteX backend. Returns resource statistics and inferred module list for FPGA targets like ice40, ecp5, and others.
Instructions
Synthesize HDL (Verilog, SystemVerilog, or VHDL) using Yosys or run LiteX backend. Provide source as: code (single string), files (dict of filename→source), or project_dir (path to HDL files on disk). Returns resource statistics and the list of inferred modules. Supported targets: generic, ice40, ecp5, gowin, xilinx, intel.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | No | HDL source code (single-file mode) | |
| files | No | Multi-file mode: mapping of filename to source code | |
| project_dir | No | Disk mode: path to directory containing HDL source files | |
| top_module | Yes | Name of the top-level module | |
| language | No | HDL language variant | verilog |
| target | No | FPGA family / synthesis target | generic |
| backend | No | Synthesis backend | yosys |
| litex_board | No | LiteX board target (required if backend=litex) | |
| litex_args | No | Extra LiteX CLI args (backend=litex) | |
| timeout | No | Timeout in seconds |