MCP server for deterministic Vivado FPGA automation including project scaffolding, simulation, synthesis, implementation, and gated bitstream generation.
A minimal MCP server that provides 25 tools and 5 hooks to control Xilinx Vivado EDA for FPGA development, including session management, Tcl execution, smart diagnostics, and IP debugging.
MCP server for AMD Xilinx Vivado 2023.1 that enables Claude Code to act as an AI FPGA engineer, providing 27 tools for querying, building, simulating, and programming FPGA designs.
A lean MCP server that lets AI agents drive Xilinx Vivado for synthesis, implementation, simulation, and diagnostics through 30 curated tools and raw Tcl execution.
Provides AI assistants with a complete FPGA toolchain for HDL linting, simulation, synthesis, and place-and-route across various hardware targets. It features a GitHub-backed IP core registry that enables users to search for and import MIT-licensed cores directly through their chat interface.