Which integrations are available for this server?

Allows AI agents to control AMD Xilinx Vivado for FPGA design, including project creation, synthesis, placement, routing, bitstream generation, simulation, and hardware programming.

How do I use Xilinx Vivado MCP?

1. Click on "Install Server". 2. Wait a few minutes for the server to deploy. Once ready, it will show a "Started" state. 3. In the chat, type @ followed by the MCP server name and your instructions, e.g., "@Xilinx Vivado MCP generate a bitstream for the current design" That's it! The server will respond to your query, and you can continue using it as needed. Here is a step-by-step guide with screenshots.

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Xilinx Vivado MCP

by zdx8637-gitdog

Overview Schema Related Servers Score Discussions

Python

Local

FPGA AI Agent Project — AX7020 Zynq-7020 Development Framework

Project Root: D:\fpgaproject Architecture: docs/architecture_ai_zynq7020.md v2.3.1 (FROZEN TOP-LEVEL) Current: B00–B09 COMPLETE; B10/O8 Freeze Package Delivered (User Confirmed GPIO v1 Stable Baseline); B11 ✅ COMPLETE (2026-08-16): Generalization Framework Black-Box Verification — Zero Peripheral Skill + 103 Tools MCP + 6-LED Test Case, White-Box/Phase Black-Box/Final Black-Box Full Chain PASS (Input Frozen at docs/development/tests/B11_phase4_blackbox_basis.md)

B03 Board Configuration Package and Environment Baseline

Sub-step	Status
0: Authoritative Asset Inventory	✅
1: Board Configuration Package and Schema	✅
2: Environment Detection and Diagnosis	✅
3: Drift and Misconfiguration Testing	✅
4: B03 General Gate and Freeze	✅
Agent2 Black-Box Acceptance	✅ (19/19 PASS)
B03 Overall	✅ COMPLETE / FROZEN

Related MCP server: vivado-mcp-agent

B04 Unified zynq_mcp Base Entry + Execution Ledger + Single-Channel Lifecycle

Sub-step	Status
R0: Architecture Audit	✅ FROZEN
R1: Skeleton + Session + Ledger + Preflight + Instance Guard	✅ COMPLETE / FROZEN (89 tests)
R2: Vivado Bridge → PL Adapter + SingleWorker + Heartbeat	✅ COMPLETE / FROZEN (35 tests, 566 collected / 565 passed / 1 skipped)
R3.0: Domain Execution Lifecycle (Command/Set/Query Runner + P9)	✅ COMPLETE / FROZEN (36 tests, 0 warnings)
R3.1-C: `pl_generate_system_top` Public Registration	✅ COMPLETE / FROZEN
Subsequent PL / PS / Verification Capabilities	✅ Integrated into unified `zynq_mcp`; Currently 101 tools total
B04 Overall	Core Lifecycle COMPLETE / FROZEN

Document	Content
B04 _pl _mcp _adapter _plan.md	B04 Implementation Plan
B04 _pl _mcp _adapter _test _plan.md	B04 Test Plan
B04 _R2 _completion _report.md	B04 R2 Completion Report
B04 _R3 _implementation _plan.md	B04 R3 PL Domain API Implementation Plan
B04 _R3 _test _plan.md	B04 R3 Test Plan

GPIO Vertical Slice Current Status

Brick	Status	Description
B07	✅ SKILL CONTRACT REMEDIATED / O6 FROZEN	Escape path removed; Agent1 completes real replay using only Skill + public MCP
B08	✅ WHITE-BOX HARDWARE PASS	Agent1 R6 completed full real hardware chain
B09	✅ COMPLETE (PUBLIC MCP BLACK-BOX PASS)	New Agent2 completes P1–P6 using only Skill + public MCP; Consistency 12/12, UART 8/8, `GPIO_E2E_PASS`, boundary and cleanup audit passed; contract errata closed
B10	✅ COMPLETE (O8 Freeze Package Delivered)	User confirmed GPIO v1 stable baseline (2026-08-14); release manifest at B10 _freeze _manifest.md; next slice direction handed over to B11
B11	✅ COMPLETE (Full Six-Phase Closure)	Generalization framework black-box verification: generalized Skill `skills/zynq_dev/`, MCP 103 tools; ③ Real board PASS, ⑤ User confirmed 6 LEDs 1s alternate, ④ Agent3 black-box PASS, ⑥ Agent2 final black-box PASS (input frozen at B11 _phase4 _blackbox _basis.md); plan at B11 _plan.md

Current O1 frozen baseline (2026-08-12): ALL_TOOLS=101; mcps 1264 collected; O1 specific 24 passed; final non-hardware regression 1225 passed / 1 skipped / 38 deselected. Additional real entry verification 12 passed; remaining 26 host/device-live not re-executed in O1.

Public MCP contract errata and remediation gates:

B09 _public _mcp _contract _erratum.md
B09 _execution _observation _contract.md — v1.0 COMPLETE / FROZEN
B09 _execution _observation _implementation _plan.md — O1–O6 COMPLETE/FROZEN; O7 R3 PASS; Errata Closed
B09 _O7 _R1 _failure _report.md — O7 Round 1 Black-Box Failure Final State, Evidence, and Re-Verification Gate
B09 _O7 _R2 _failure _report.md — O7 Round 2 Failure Evidence and Remediation After Advancing to bitstream Manifest Gate
B09 _O7 _R3 _pass _report.md — O7 Round 3 Full Public MCP Black-Box Pass Evidence, Boundary Audit, and Cleanup Results
B09 _O1 _completion _report.md — Ledger v2 Compatible Extension Implementation and Layered Regression Evidence
B09 _O2 _implementation _report.md — O2 Freeze Evidence: Unified EDA Backend Ownership, Real PID/PROCESS Observation, and Regression
B09 _O3 _implementation _report.md — O3 Freeze Evidence: Platform/PL Real Vivado STATUS Observation and Manifest Final Gate
B09 _O4 _implementation _report.md — O4 Freeze Evidence: XSCT Real PID/Step Observation, ARM ELF and PS Manifest Final Gate
B09 _O5 _implementation _report.md — O5 Freeze Evidence: Controller-owned XSDB, JTAG lease, UART capture, and Real RESOURCE Observation
B09 _O6 _completion _report.md — O6 Freeze Evidence: Skill Public Boundary, Agent1 Full Public MCP Real GPIO Replay, and Cleanup
Original B09 hardware evidence retained in workspaces/gpio_b09_r3_20260812/REPORT_B09_R3_Agent2.md

Development Planning Documents

Document	Content
B03 _completion _report.md	B03 Completion Report
B03 _to _B04 _handoff.md	B03→B04 Handoff
B03 _asset _inventory.md	B03 Sub-step 0 Asset Inventory

Entry Documents

Document	Content
architecture _ai _zynq7020.md	Frozen Top-Level Architecture: Three Domains Four Layers + P1-P8
brick _development _plan.md	Brick Development Plan and Progress
B00 _project _cleanup _plan.md	B00 Project Cleanup Plan (v0.3)
B00 _completion _report.md	B00 Execution Report

Core Components

Directory	Description
`Xilinx_Vivado_MCP/`	Vivado MCP Server (27 tools + 2 Skills), Independent Git Repository
`Xilinx_Vitis_MCP/`	Vitis MCP Server Skeleton, Independent Git Repository
`zynq_platforms/`	AX7020 Platform Project, Independent Git Repository
`docs/`	Architecture Documents, Development Records, Vendor Tutorials
`tools/scripts/`	Utility Scripts (UART Scan, Driver Installation)
`vendor/drivers/`	Vendor Drivers (CP210x, FTDI)

Reference Designs

Directory	Description
`hello_fpga/`	Pure PL Breath LED Complete Project
`g9_hw_test/`	PL Hardware Closed-Loop Verification
`embedded_projects/`	PS Bare-Metal ARM Reference Code
`validation_projects/`	Golden + 11 Fault Injections + Agent2 Black-Box

External Materials

Path	Description
`docs/boardinformation/`	ALINX Official 6 PDF Tutorials (~99MB)
`vendor/drivers/`	CP210x/FTDI USB Drivers

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