Allows AI agents to control AMD Xilinx Vivado for FPGA design, including project creation, synthesis, placement, routing, bitstream generation, simulation, and hardware programming.
Click on "Install Server".
Wait a few minutes for the server to deploy. Once ready, it will show a "Started" state.
In the chat, type @ followed by the MCP server name and your instructions, e.g., "@Xilinx Vivado MCP generate a bitstream for the current design"
That's it! The server will respond to your query, and you can continue using it as needed.
Here is a step-by-step guide with screenshots.
MCP (Model Context Protocol) server for AMD Xilinx Vivado 2023.1. Enables Claude Code to operate as an AI FPGA engineer.
Layer 3: Workflow (Skills: fpga-verify, fpga-develop)
Layer 2: Tool (27 MCP Tools)
Layer 1: Process (VivadoProcess, XSimProcess)Related MCP server: vivado-mcp-agent
Install Vivado 2023.1 at D:\Xilinx\Vivado\2023.1
Create Python venv: python -m venv .venv && .venv\Scripts\pip install -r requirements.txt
Register in Claude Code via .mcp.json
Category | Tools |
Query (7) | get_vivado_info, get_capabilities, get_cells, get_nets, get_clocks, get_ports, get_property |
Project (2) | open_checkpoint, close_design |
Analysis (2) | report_timing_summary, report_utilization |
Build (5) | create_project, synth_design, place_design, route_design, write_bitstream |
Simulation (4) | compile_sim, elaborate_sim, run_simulation, parse_sim_log |
Validation (1) | validate_design |
Hardware (5) | connect_hw_server, get_device_status, program_device, read_uart, list_serial_ports |
Admin (1) | run_tcl |
fpga-verify — Complete design verification workflow
fpga-develop — Iterative development with diagnosis and repair
XC7Z020CLG400-2 (ALINX AX7020), Vivado 2023.1
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