Lint HDL source code using iverilog/verilator (Verilog/SystemVerilog) or ghdl (VHDL). Use linter='verilator' to enable -Wall checks including multidriven net detection.

Lint multiple HDL files together so cross-module references resolve. Pass a dict of filename-to-source pairs. All files are compiled in one invocation of iverilog/verilator (Verilog/SystemVerilog) or ghdl (VHDL). Use linter='verilator' to enable -Wall checks including multidriven net detection.

Synthesize HDL (Verilog, SystemVerilog, or VHDL) using Yosys or run LiteX backend. Provide source as: code (single string), files (dict of filename→source), or project_dir (path to HDL files on disk). Returns resource statistics and the list of inferred modules. Supported targets: generic, ice40, ecp5, gowin, xilinx, intel.

Synthesize HDL with Yosys then place-and-route with nextpnr in one step. Provide source as: code (single string), files (dict of filename→source), or project_dir (path to HDL files on disk). If backend=litex, runs LiteX build and ignores HDL inputs. Returns max frequency, critical path, resource utilization, bitstream, and full logs. Supported targets: ice40, ecp5, nexus, gowin. Common device/package values: ice40: device=hx1k|hx8k|up5k|lp1k package=tq144|qn84|sg48|cm81 ecp5: device=25k|45k|85k package=CABGA256|CABGA381 nexus: device=LIFCL-40-9BG400C (package embedded in device string) gowin: device=GW1N-UV4LQ144C6/I5 (package embedded in device string)

Compile and simulate HDL using Icarus Verilog (iverilog + vvp) or GHDL (VHDL). Provide the design source and a separate testbench. Returns all $display/$monitor output (Verilog) or report output (VHDL) and any runtime errors.

List all available IP cores in the registry. Optionally filter by category.

Fetch the full manifest and HDL source files for a named IP core.

Search GitHub for open-source FPGA IP cores (MIT, BSD, Apache, GPL, etc). Returns repo names, star counts, descriptions and topics. Use import_github_core to download a result into the local registry.

Download an open-source GitHub repository and add it to the local IP core registry. Automatically uses FuseSoC CAPI2 metadata (.core file) if one exists in the repo. After import, the core is immediately available via get_ip_core and generate_ip.

Import a local FuseSoC CAPI2 .core file into the registry. HDL files referenced in the .core file must exist in the same directory. Useful when you already have FuseSoC cores checked out locally.

Generate a parameterized instance of an IP core. Returns the HDL source files and a ready-to-paste Verilog instantiation snippet with the requested parameter values applied.

Return structured lint diagnostics (line, column, severity, message) for HDL source. Verilog/SystemVerilog: uses Verilator (primary) with verible-verilog-lint as fallback. VHDL: uses GHDL. All tools are part of OSS CAD Suite.

Format HDL source code and return the result. Verilog/SystemVerilog: uses verible-verilog-format. VHDL: uses vsg (pip install vsg). Returns the formatted code and whether it changed.

Run LiteX board target with --build. Returns logs and output directory.

Generate LiteX SoC without building gateware. Returns logs and output directory.

Run a generic LiteX board target with caller-provided args.

Start a long-running build command in the background. Returns a build_id to check progress with build_status. Use for synthesis, place-and-route, LiteX builds, or any command that takes minutes.

Check the progress of a background build. Returns status (running/success/failed), elapsed time, and recent log output.

List all tracked builds (running and finished) with status summary.

Cancel a running background build.

Check which EDA tools are installed and reachable. Returns tool name, path, and version for each detected binary.

Re-scan all core directories and rebuild the IP core cache. Call after adding cores to disk or editing config.json.

Delete old build logs to reclaim disk space. Removes logs older than max_age_days, then trims oldest until under max_total_mb.

Flash a bitstream to an FPGA board using iceprog (ice40) or openFPGALoader (ecp5/gowin/nexus). Provide bitstream as base64 (from place_and_route output) or a file path on disk.

List all known FPGA board presets with target, device, package, and clock frequency.