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lcapossio

fpgaZeroMCP

by lcapossio

format_hdl

Formats Verilog, SystemVerilog, or VHDL source code using verible-verilog-format or vsg, returning the formatted result and change status.

Instructions

Format HDL source code and return the result. Verilog/SystemVerilog: uses verible-verilog-format. VHDL: uses vsg (pip install vsg). Returns the formatted code and whether it changed.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
codeYesHDL source code to format
languageNoHDL language variantverilog
Behavior3/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

The description discloses that the tool returns formatted code and a change indicator, and names the underlying formatters. However, since no annotations are provided, the description bears full burden; it does not explicitly state whether the tool modifies files or is read-only, nor does it cover potential side effects.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness5/5

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is concise: three sentences front-load the main action and provide key details without redundancy. Every sentence adds value.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness4/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

With only two parameters having full schema coverage and no output schema, the description explains the return value and underlying tools. It could mention installation requirements or side effects but is sufficiently complete for a low-complexity tool.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters3/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

The input schema covers both parameters with descriptions (100% coverage). The description adds context about the formatters used per language but does not provide additional semantic details beyond the schema, warranting a baseline score of 3.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

The description clearly states the tool's purpose: formatting HDL source code and returning the result. It specifies the tools used for Verilog/SystemVerilog and VHDL, distinguishing it from sibling tools like lint_hdl and synthesize.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines3/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description implies that the tool should be used to format HDL code but provides no explicit guidance on when to use it versus alternatives like lint_hdl for linting. No exclusions or prerequisites are mentioned.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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