format_hdl
Formats Verilog, SystemVerilog, or VHDL source code using verible-verilog-format or vsg, returning the formatted result and change status.
Instructions
Format HDL source code and return the result. Verilog/SystemVerilog: uses verible-verilog-format. VHDL: uses vsg (pip install vsg). Returns the formatted code and whether it changed.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"code": "<code>"
},
"name": "format_hdl"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL source code to format | |
| language | No | HDL language variant | verilog |