get_diagnostics
Analyze HDL source code for lint errors and warnings. Returns line, column, severity, and message for Verilog, SystemVerilog, and VHDL.
Instructions
Return structured lint diagnostics (line, column, severity, message) for HDL source. Verilog/SystemVerilog: uses Verilator (primary) with verible-verilog-lint as fallback. VHDL: uses GHDL. All tools are part of OSS CAD Suite.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"code": "<code>"
},
"name": "get_diagnostics"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL source code | |
| language | No | HDL language variant | verilog |