generate_ip
Generates HDL source files and a Verilog instantiation snippet for a parameterized IP core, applying specified parameter overrides.
Instructions
Generate a parameterized instance of an IP core. Returns the HDL source files and a ready-to-paste Verilog instantiation snippet with the requested parameter values applied.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"name": "<name>"
},
"name": "generate_ip"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| name | Yes | Core name, e.g. 'uart_tx' or 'fifo' | |
| parameters | No | Parameter overrides, e.g. {"CLKS_PER_BIT": 434} | |
| instance_name | No | Verilog instance name (default: <core_name>_inst) |