place_and_route
Synthesize HDL code with Yosys and perform place-and-route with nextpnr for FPGA targets like ice40, ecp5, nexus, and gowin. Returns bitstream, timing, and resource usage.
Instructions
Synthesize HDL with Yosys then place-and-route with nextpnr in one step. Provide source as: code (single string), files (dict of filename→source), or project_dir (path to HDL files on disk). If backend=litex, runs LiteX build and ignores HDL inputs. Returns max frequency, critical path, resource utilization, bitstream, and full logs. Supported targets: ice40, ecp5, nexus, gowin. Common device/package values: ice40: device=hx1k|hx8k|up5k|lp1k package=tq144|qn84|sg48|cm81 ecp5: device=25k|45k|85k package=CABGA256|CABGA381 nexus: device=LIFCL-40-9BG400C (package embedded in device string) gowin: device=GW1N-UV4LQ144C6/I5 (package embedded in device string)
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | No | HDL source code (single-file mode) | |
| files | No | Multi-file mode: mapping of filename to source code | |
| project_dir | No | Disk mode: path to directory containing HDL source files | |
| top_module | Yes | Top-level module name | |
| language | No | HDL language variant | verilog |
| target | No | FPGA family | |
| device | No | Device variant, e.g. 'hx1k', '25k', 'LIFCL-40-9BG400C' | |
| package | No | Package, e.g. 'tq144', 'CABGA256' (not needed for nexus/gowin) | |
| constraints | No | Optional pin constraints (PCF/LPF/PDC/CST text) | |
| timeout | No | PnR timeout in seconds | |
| backend | No | PnR backend | yosys |
| litex_board | No | LiteX board target (required if backend=litex) | |
| litex_args | No | Extra LiteX CLI args (backend=litex) | |
| board | No | Board preset (e.g. 'icebreaker', 'ulx3s_85f'). Sets target/device/package/clock automatically. | |
| nextpnr_args | No | Extra nextpnr arguments (e.g. ['--seed', '42', '--placer', 'heap']) | |
| work_dir | No | Persistent working directory for incremental runs. Returned in response for reuse. |