simulate
Compile and simulate HDL designs with Icarus Verilog or GHDL. Provide design code and testbench to get simulation output and runtime errors.
Instructions
Compile and simulate HDL using Icarus Verilog (iverilog + vvp) or GHDL (VHDL). Provide the design source and a separate testbench. Returns all $display/$monitor output (Verilog) or report output (VHDL) and any runtime errors.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL design source | |
| testbench | Yes | HDL testbench source | |
| language | No | HDL language variant | verilog |
| timeout | No | Timeout in seconds |