lint_hdl
Lint Verilog, SystemVerilog, and VHDL code. Use verilator backend to enable -Wall checks including multidriven net detection.
Instructions
Lint HDL source code using iverilog/verilator (Verilog/SystemVerilog) or ghdl (VHDL). Use linter='verilator' to enable -Wall checks including multidriven net detection.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL source code to lint | |
| language | No | HDL language variant | verilog |
| top_module | No | Top-level module name (optional) | |
| linter | No | Linter backend for Verilog/SV. 'verilator' enables -Wall (multidriven nets, etc.) | iverilog |