lint_hdl
Lint Verilog, SystemVerilog, and VHDL code. Use verilator backend to enable -Wall checks including multidriven net detection.
Instructions
Lint HDL source code using iverilog/verilator (Verilog/SystemVerilog) or ghdl (VHDL). Use linter='verilator' to enable -Wall checks including multidriven net detection.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"code": "<code>"
},
"name": "lint_hdl"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL source code to lint | |
| language | No | HDL language variant | verilog |
| top_module | No | Top-level module name (optional) | |
| linter | No | Linter backend for Verilog/SV. 'verilator' enables -Wall (multidriven nets, etc.) | iverilog |