lint_project
Lint multiple HDL files together to resolve cross-module references, supporting Verilog, SystemVerilog, and VHDL with optional -Wall checks via verilator.
Instructions
Lint multiple HDL files together so cross-module references resolve. Pass a dict of filename-to-source pairs. All files are compiled in one invocation of iverilog/verilator (Verilog/SystemVerilog) or ghdl (VHDL). Use linter='verilator' to enable -Wall checks including multidriven net detection.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| files | Yes | Mapping of filename to source code, e.g. {"uart_tx.v": "module uart_tx...", "top.v": "module top..."} | |
| language | No | HDL language variant | verilog |
| top_module | No | Top-level module name (optional) | |
| timeout | No | Timeout in seconds | |
| linter | No | Linter backend for Verilog/SV. 'verilator' enables -Wall (multidriven nets, etc.) | iverilog |