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ILA: 发现可抽头的真实网名(综合→解析网表)

fpga_ila_list_nets

Lists flattened, hierarchical scalar net names accepted by Fabric Inserter after synthesis, resolving RTL-name mismatches; optionally expands buses and verifies signals in an isolated compile to prevent ILA insertion failures.

Instructions

解决 ILA 抽头的根本问题:综合 flatten 后的网名 ≠ RTL 名。本工具在隔离旁路副本中 compile→run_ads,再调用 Fabric Inserter 的 ins_list_nets 取得 .fic 真正可消费的全层级标量网名;不会从模块定义猜路径。可选 signals 会展开唯一总线并返回 exact/renamed/hierarchical/ambiguous/unverified/pruned,多实例同名必须传完整层级。fpga_ila_build 使用同一权威清单做 FIC 前 fail-fast。

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
pdsPathYes.pds 工程绝对路径(已含 RTL/约束;器件从工程读取)
signalsNo可选:把期望 RTL 名或完整 flattened 名解析为 Inserter 真网名;唯一总线自动按位展开,多实例同名回 ambiguous+candidates
pdsVersionNo可选 PDS 版本标签(定位 pds_shell);省略按工程器件选择
timeoutSecNo综合超时秒数,默认 300
Behavior5/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations provided, the description carries the full burden and delivers: it discloses that the tool runs compile→run_ads inside an isolated bypass copy (side-effect containment), triggers a full synthesis (justifying timeoutSec), obtains names via ins_list_nets from the .fic, and states a key limitation — it does not guess paths from module definitions. It also reveals the output status taxonomy (exact/renamed/hierarchical/ambiguous/unverified/pruned) and the ambiguous+candidates behavior for multi-instance nets.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness5/5

Is the description appropriately sized, front-loaded, and free of redundancy?

Three dense sentences with the core purpose front-loaded ('solves the fundamental ILA probing problem'), followed by mechanism, optional behavior, and workflow relationship. Every clause carries distinct information — problem, mechanism, limitation, statuses, and fpga_ila_build dependency — with no filler or repetition.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness5/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a tool with no annotations and no output schema, the description is remarkably complete: it covers purpose, mechanism, side effects (isolated copy, full synthesis run), parameter nuances, return status categories, and its place in the ILA flow. An agent has enough to decide when to call it, what to pass, and what shape of result to expect.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters4/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema coverage is 100%, establishing a baseline of 3. The description adds meaning beyond the schema for the signals parameter by listing the full resolution status taxonomy not present in the schema, and it gives context to pdsPath/timeoutSec by explaining the isolated compile→run_ads flow. It does not add novel format details for pdsVersion or timeoutSec beyond what the schema already states.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

States a precise verb and resource: it discovers the real, probe-able full-hierarchy scalar net names that the Fabric Inserter can consume from the .fic, explicitly distinguishing them from RTL names. It differentiates itself from siblings by declaring it does not guess paths from module definitions and by positioning fpga_ila_build as the consumer of the same authoritative list.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines4/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

Provides clear situational context — use it when post-synthesis flattened net names diverge from RTL names and you need the exact names the Inserter will consume — and establishes the workflow position (fpga_ila_build uses the same list for FIC fail-fast). It also gives conditional guidance for signals (unique buses auto-expand; multi-instance same-name nets require full hierarchy), but it never explicitly names an alternative tool or states when not to use this one.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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