仿真断言判定
fpga_assertRun declarative assertions on FPGA simulation logs and VCD waveforms to verify expected behavior and catch mismatches automatically.
Instructions
对 fpga_sim 日志和/或 VCD 做声明式断言判定。支持日志包含/正则与 VCD 终值/指定时刻/永不等于。
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| log | No | 仿真日志文本 | |
| vcdPath | No | VCD 文件绝对路径 | |
| knowledge | No | 可选:仅当客观验证全绿时自动写回 knowledge-vault candidate;调用方不能自报 pass/fail | |
| assertions | Yes | 断言列表 |