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ILA: 生成 .fic 配置(纯本地代码生成,低层原语)

fpga_ila_generate_fic

Generate a Pango .fic file for ILA by writing the target device, clock net, and post-synthesis signal names. Resolve real net names with fpga_ila_list_nets first to avoid RTL name mismatches.

Instructions

低层原语:把器件 + 时钟网 + 信号网名清单写成符合 Pango .fic 规范的文本。入参必须是综合后真实网名——flatten 会改名(寄存器 tx→nt_led[0]、时钟 clk→nt_clk),勿假设 RTL 名保留;不知真名先用 fpga_ila_list_nets,或直接用 fpga_ila_build(接受期望名并自动解析)。生成后用 fpga_pds_register_fic 注册→fpga_pds_run gen_bit_stream 出仪表化 sbit。

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
partYes完整目标器件 family/device/speedgrade/package(板级物理信息,来自工程/用户/Target Profile,工具不默认、不猜)
ficPathYes.fic 输出绝对路径(建议 <projectDir>/debug/<name>.fic)
signalsYes要抓的信号网名清单(综合后真实网名;RTL 名未必保留,用 fpga_ila_list_nets 解析)
clockNetYes采样时钟网名(综合后真实网名,如 nt_clk/clk_g;用 fpga_ila_list_nets 的 clocks 取)
busGroupsNo可选显示分组(数据 bus 在波形里整体显示)
dataDepthNo采样深度,默认 1024(消耗 DRM 块)
designInputFileNo可选:综合网表/.adf 绝对路径,写入 .fic 的 designInputFile 字段;一般留空由工程上下文提供
Behavior4/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

No annotations are provided, so the description carries the full burden of behavioral disclosure. It does this well by warning about flatten renaming, requiring post-synthesis net names, and framing the tool as pure local code generation. It does not mention edge behaviors like file overwrite or validation failure, but the critical behavioral constraints are clearly disclosed.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness5/5

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is dense but well structured: core action, then critical caveat, then alternatives, then downstream workflow. Every sentence contributes actionable information, and there is no filler or repetition of schema content.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness5/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a 7-parameter tool with nested objects and no output schema, the description covers the essential usage context: what input is required, why the input must be real net names, how to obtain those names, which alternative tool to prefer, and what to do after generation. Combined with the fully-described schema, an agent has enough to invoke the tool correctly.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters4/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema coverage is 100%, so the baseline is 3. The description adds meaningful semantics beyond the schema by explaining that signals and clockNet must be post-synthesis real net names, giving concrete rename examples, and directing the agent to fpga_ila_list_nets for resolution. It does not discuss busGroups or dataDepth in prose, but those are already well covered by schema descriptions.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

The description names a specific action — writing device, clock net, and signal net names into a Pango .fic text file — and identifies itself as a low-level primitive. It clearly distinguishes itself from fpga_ila_build and fpga_ila_list_nets, so an agent can tell this tool apart without inspecting schemas.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines5/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description explicitly states when to use this tool: when you already have post-synthesis real net names. It also gives clear alternatives: use fpga_ila_list_nets if names unknown, or use fpga_ila_build for automatic name resolution. It even names the downstream sequence (fpga_pds_register_fic → fpga_pds_run gen_bit_stream), which fully orients the agent.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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