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ILA: 仪表化构建(生成 .fic→注册→gen_bit_stream)→ sbit + 构建报告网页

fpga_ila_build

Build ILA instrumentation in one call: resolve signals, validate before generating .fic/bitstream, and fail-fast on ambiguous or optimized nets. Returns sbit+fic+report for JTAG flash and capture.

Instructions

把 ILA 仪表化构建合并成一次自纠调用:旁路综合→Fabric Inserter ins_list_nets 权威解析→FIC 前精确成员校验→生成/注册 .fic→gen_bit_stream。多实例同名回 ambiguous,未被 Inserter 验证或已优化的信号都会在修改工程前 fail-fast。返回 sbit+fic+报告;本地默认把 sbit 交给 fpga_jtag_flash,再把 fic 交给 fpga_jtag_capture。GUI flow 仅作远程/特殊功能 fallback。

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
hostNo远程构建 host id(省略=本机)。注意:网名发现在本机综合(与板无关),gen_bit_stream 才用 host。
ficPathNo.fic 输出路径,默认 <projectDir>/debug/ila.fic
pdsPathYes.pds 工程绝对路径(已含 RTL/约束;器件从工程读取)
signalsYes要抓的期望 RTL 名或 Inserter 完整网名。唯一总线自动按位展开;多实例同名必须传完整层级;未验证/被优化会在写 FIC 前失败。
clockNetNo采样时钟的 RTL 名或 Inserter 完整网名;省略时从已发现且经 Inserter 验证的时钟候选中取第一个。
busGroupsNo显示分组,如 [{name:'counter',low:0,high:15}]
dataDepthNo采样深度,默认 1024
reportDirNo构建报告网页输出目录,默认 ~/fpga-ila-captures
pdsVersionNo可选 PDS 版本/标签,如 2022.2 或 2025.2;省略按工程器件选择
Behavior5/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations provided, the description carries the full behavioral disclosure burden, and it does so well. It reveals fail-fast behavior for ambiguous, unverified, or optimized signals, states that validation happens before modifying the project, and exposes side effects by saying the sbit is handed to fpga_jtag_flash and the fic to fpga_jtag_capture by default. This goes beyond the schema and gives the agent a realistic model of what the tool will do.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness4/5

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is dense but efficient: every sentence adds substantive information about pipeline, validation behavior, outputs, or fallback. The core pipeline is front-loaded in the first sentence. A small amount of structure, such as bullet points or clearer separation between pipeline, error behavior, and defaults, would improve readability, but there is no fluff.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness4/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a complex tool with 9 parameters, no annotations, and no output schema, the description covers the essential behavioral contract: pipeline steps, outputs, side effects, default downstream actions, and error-handling posture. The input schema fully covers parameter details. The main gap is that the exact structure of the returned report and sbit/fic result is not described, and explicit differentiation from fpga_ila_flow is only implicit.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters4/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is 100%, so the baseline is 3. The description adds meaningful parameter-related context beyond the schema, especially for the signals parameter: multi-instance same-name ambiguity returns 'ambiguous', and unverified/optimized signals cause fail-fast before the project is modified. This helps the agent construct valid inputs, though not every parameter receives additional explanation.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

The description clearly states the core function: combining ILA instrumented build into one self-correcting call, with a concrete pipeline (bypass synthesis → ins_list_nets parsing → FIC validation → generate/register .fic → gen_bit_stream). It also names concrete outputs (sbit+fic+报告), making the tool's purpose distinct from the individual-step sibling tools like fpga_ila_generate_fic and fpga_ila_list_nets.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines4/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description gives clear context for when to use this tool: it is the consolidated local build path, and GUI flow is explicitly positioned as only a remote/special fallback. It also mentions default chaining to fpga_jtag_flash and fpga_jtag_capture, which helps the agent understand the tool's role in the broader flow. However, it does not explicitly name sibling alternatives such as fpga_ila_flow as the thing to use instead in other scenarios.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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