update_project
Modify FPGA project files by adding or removing HDL and SDC files, changing the top module or device, with a backup created automatically.
Instructions
Edit a project .xml: add or remove HDL files and SDC files, change the top module or the device. A .xml.bak backup is written first.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| device | No | ||
| family | No | ||
| add_sdc | No | ||
| project | Yes | ||
| add_files | No | ||
| remove_sdc | No | ||
| top_module | No | ||
| remove_files | No | ||
| timing_model | No |