get_utilization
Check FPGA resource usage after place and route, including core and periphery utilization, with an optional per-module breakdown to identify resource consumption by hierarchy.
Instructions
Resource usage: core (XLRs, memory, DSP, I/O, clocks) and periphery after place & route, plus synthesis estimates. hierarchy=True adds a per-module breakdown (values are total(self)).
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| project | Yes | ||
| hierarchy | No | ||
| max_depth | No |