edit_interface
Modify FPGA interface designs (.peri.xml) by applying GPIO, PLL, pin, and property operations with validation, backup, and optional dry-run.
Instructions
Change the Interface Designer design (.peri.xml). Operations run in order; if any fails, nothing is saved. After the operations the design check runs, and the file is saved only if no new design-check errors appeared (allow_new_errors=True saves anyway). dry_run=True applies and checks without saving. A .peri.xml.bak backup is written before saving. If the project has no .peri.xml yet, one is created for the project's device.
Values are validated against the allowed values (see get_interface_block); I/O standards may be written as '3.3 V LVCMOS' or '3.3_V_LVCMOS'.
Operations (each is an object with "op"): {"op": "create_gpio", "name": "led", "mode": "output", "pin": "U4", "properties": {"IO_STANDARD": "1.8 V LVCMOS"}} mode: input | output | inout | open_drain_output | clock_input | regional_clock_input | pll_clock_input | pll_ext_feedback | mipi_clock_input | pcie_perstn | clockout | global_control | vref | unused. A bus: add "msb": 7, "lsb": 0 (input/output/inout); buses can't take "pin", so place members with assign_pin on "led[0]" etc. "resource" (e.g. "GPIOB_P_31") can be given instead of "pin". {"op": "create_block", "name": "pll0", "type": "PLL", "resource": "PLL_TL0", "properties": {...}} type: any of block_types_supported from get_interface_design (PLL, OSC, LVDS_TX, LVDS_RX, MIPI_DPHY_RX, DDR, JTAG, PMA_DIRECT, ...). Optional "params" are passed to the API's create_block (tx_mode / rx_conn_type for LVDS, mode / conn_type for MIPI lanes). {"op": "set_properties", "name": "led", "properties": {"PULL_OPTION": "WEAK_PULLUP", "DRIVE_STRENGTH": "8"}} On a bus name, sets every member. Add "type" if a name is ambiguous. {"op": "assign_pin", "name": "led", "pin": "U4"} (GPIO package ball) {"op": "assign_resource", "name": "pll0", "resource": "PLL_TR1"} Both refuse a resource already used by another instance unless "override": true. {"op": "delete", "name": "old_sig"} {"op": "set_bank_voltage", "bank": "4B", "voltage": "1.8"} {"op": "auto_calc_pll", "name": "pll0", "targets": {"CLKOUT0_FREQ": 200, "CLKOUT1_FREQ": 100}} Solves and applies M/N/O and dividers. Enable the outputs first (CLKOUTn_EN=1, CLKOUTn_PIN). PLL output frequencies are read-only properties; this is how they are set. {"op": "gen_pll_ref_clock", "name": "pll0", "refclk_name": "pll_refclk", "pll_res": "PLL_TL0"} Creates the reference-clock GPIO on the pin that feeds that PLL. {"op": "set_unused_gpio_state", "state": "INPUT_WITH_WEAK_PULLUP"} {"op": "import_isf", "file": "C:/path/settings.isf"} (Interface Scripting File)
After saving, run_flow(compile) rebuilds with the new interface. If the project is open in the Efinity GUI, close it or reload it there, or the GUI may save its old copy over these changes.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| dry_run | No | ||
| project | Yes | ||
| operations | Yes | ||
| allow_new_errors | No |