get_interface_design
Retrieves the saved Interface Designer configuration for an FPGA project, listing GPIO settings, block resources, and I/O bank voltages. Optionally filter by block type or run the design check to validate the design.
Instructions
Overview of the project's Interface Designer (.peri.xml) design: every GPIO (mode, I/O standard, resource, package pin, bank), every other block (PLL, OSC, LVDS, MIPI, DDR, JTAG, PMA_DIRECT, ...) with its resource and key settings, and the I/O bank voltages.
block_types limits the listing (e.g. ["GPIO"] or ["PLL"]). include_check also runs the Interface Designer design check. Reads the saved file, so it reflects the GUI only after the GUI saves.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| project | Yes | ||
| block_types | No | ||
| include_check | No |