create_project
Initialize an Efinity FPGA project by configuring family, device, timing model, and design files, enabling immediate compilation.
Instructions
Create a new Efinity project .xml.
family: Trion | Titanium | Topaz. device: e.g. Ti375N1156, Ti60F225, T20F256.
timing_model: speed grade such as C4, C3, I4. design_files and sdc_files may be absolute or
relative to directory. verilog_version: verilog_2k | sv_09 | ...; vhdl_version: vhdl_2008 | vhdl_93.
The Interface Designer file (.peri.xml) is created by the first edit_interface call
(create the GPIOs / PLLs the top module's ports need) before a full compile.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| name | Yes | ||
| device | Yes | ||
| family | Yes | ||
| directory | Yes | ||
| sdc_files | No | ||
| top_module | Yes | ||
| design_files | Yes | ||
| timing_model | Yes | ||
| vhdl_version | No | vhdl_2008 | |
| verilog_version | No | verilog_2k |