synthesize
Synthesize Verilog HDL code for FPGA targets using Yosys or LiteX backend to generate resource statistics and module lists.
Instructions
Synthesize Verilog HDL using Yosys or run LiteX backend. Returns resource statistics and the list of inferred modules. Supported targets: generic, ice40, ecp5, gowin, xilinx, intel.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | Verilog source code | |
| top_module | Yes | Name of the top-level module | |
| target | No | FPGA family / synthesis target | generic |
| backend | No | Synthesis backend | yosys |
| litex_board | No | LiteX board target (required if backend=litex) | |
| litex_args | No | Extra LiteX CLI args (backend=litex) | |
| timeout | No | Timeout in seconds |