get_diagnostics
Analyze HDL source code to identify lint issues with line, column, severity, and message details for Verilog, SystemVerilog, or VHDL using industry-standard tools.
Instructions
Return structured lint diagnostics (line, column, severity, message) for HDL source. Verilog/SystemVerilog: uses Verilator (primary) with verible-verilog-lint as fallback. VHDL: uses GHDL. All tools are part of OSS CAD Suite.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL source code | |
| language | No | HDL language variant | verilog |