lint_hdl
Analyze Verilog, SystemVerilog, or VHDL code to identify syntax errors and warnings before synthesis, helping ensure hardware designs are correct.
Instructions
Lint HDL source code using iverilog (Verilog/SystemVerilog) or ghdl (VHDL). Returns warnings and errors so you can fix them before synthesis.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL source code to lint | |
| language | No | HDL language variant | verilog |
| top_module | No | Top-level module name (optional) |