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lint_hdl

Analyze Verilog, SystemVerilog, or VHDL code to identify syntax errors and warnings before synthesis, helping ensure hardware designs are correct.

Instructions

Lint HDL source code using iverilog (Verilog/SystemVerilog) or ghdl (VHDL). Returns warnings and errors so you can fix them before synthesis.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
codeYesHDL source code to lint
languageNoHDL language variantverilog
top_moduleNoTop-level module name (optional)

Implementation Reference

  • The handler function that executes the lint_hdl tool logic. It lints HDL source code using iverilog (Verilog/SystemVerilog) or ghdl (VHDL), creates a temporary file with the code, runs the appropriate linter, and returns success status with output/errors.
    def lint_hdl(
        code: str,
        language: str = "verilog",
        top_module: str | None = None,
    ) -> dict:
        """Lint HDL source using iverilog (Verilog/SV) or ghdl (VHDL)."""
        suffix_map = {
            "verilog": ".v",
            "systemverilog": ".sv",
            "vhdl": ".vhd",
        }
        suffix = suffix_map.get(language, ".v")
    
        with tempfile.NamedTemporaryFile(suffix=suffix, mode="w", delete=False) as f:
            f.write(code)
            tmpfile = f.name
    
        try:
            if language == "vhdl":
                cmd = ["ghdl", "-a", "--std=08", tmpfile]
            elif language == "systemverilog":
                cmd = ["iverilog", "-g2012", "-tnull", tmpfile]
            else:
                cmd = ["iverilog", "-tnull", tmpfile]
    
            result = subprocess.run(cmd, capture_output=True, text=True, timeout=30)
    
            output = {
                "success": result.returncode == 0,
                "tool": cmd[0],
                "language": language,
                "stdout": result.stdout,
                "stderr": result.stderr,
            }
            if result.returncode == 0:
                output["message"] = "No errors found."
            return output
    
        except FileNotFoundError:
            tool = "ghdl" if language == "vhdl" else "iverilog"
            return {
                "success": False,
                "error": f"'{tool}' not found. Install it and ensure it is on PATH.",
            }
        except subprocess.TimeoutExpired:
            return {"success": False, "error": "Lint timed out after 30 s."}
        finally:
            os.unlink(tmpfile)
  • Input schema definition for the lint_hdl tool, defining the expected parameters: 'code' (required), 'language' (enum: verilog/systemverilog/vhdl, default: verilog), and 'top_module' (optional).
    inputSchema={
        "type": "object",
        "properties": {
            "code":     {"type": "string", "description": "HDL source code to lint"},
            "language": {
                "type": "string",
                "enum": ["verilog", "systemverilog", "vhdl"],
                "default": "verilog",
                "description": "HDL language variant",
            },
            "top_module": {"type": "string", "description": "Top-level module name (optional)"},
        },
        "required": ["code"],
    },
  • server.py:31-51 (registration)
    Tool registration where lint_hdl is defined as a types.Tool with name, description, and inputSchema. This is part of the handle_list_tools() function that returns all available tools.
    types.Tool(
        name="lint_hdl",
        description=(
            "Lint HDL source code using iverilog (Verilog/SystemVerilog) or ghdl (VHDL). "
            "Returns warnings and errors so you can fix them before synthesis."
        ),
        inputSchema={
            "type": "object",
            "properties": {
                "code":     {"type": "string", "description": "HDL source code to lint"},
                "language": {
                    "type": "string",
                    "enum": ["verilog", "systemverilog", "vhdl"],
                    "default": "verilog",
                    "description": "HDL language variant",
                },
                "top_module": {"type": "string", "description": "Top-level module name (optional)"},
            },
            "required": ["code"],
        },
    ),
  • Dispatch handler for lint_hdl that extracts arguments and calls the lint_hdl function asynchronously via asyncio.to_thread, passing code, language, and top_module parameters.
    case "lint_hdl":
        result = await asyncio.to_thread(
            lint_hdl,
            code=arguments["code"],
            language=arguments.get("language", "verilog"),
            top_module=arguments.get("top_module"),
        )

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