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lint_hdl

Analyze Verilog, SystemVerilog, or VHDL code to identify syntax errors and warnings before synthesis, helping ensure hardware designs are correct.

Instructions

Lint HDL source code using iverilog (Verilog/SystemVerilog) or ghdl (VHDL). Returns warnings and errors so you can fix them before synthesis.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
codeYesHDL source code to lint
languageNoHDL language variantverilog
top_moduleNoTop-level module name (optional)
Behavior3/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations provided, the description carries the full burden of behavioral disclosure. It describes the tool's function (linting), tools used (iverilog/ghdl), and output (warnings/errors), but lacks details on error handling, performance, or side effects. It doesn't contradict annotations, but could benefit from more behavioral context.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness5/5

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is front-loaded and concise with two sentences that efficiently convey purpose, method, and outcome. Every sentence earns its place without redundancy, making it easy for an AI agent to parse quickly.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness3/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

Given no annotations and no output schema, the description adequately covers the tool's purpose and basic behavior. However, for a tool with 3 parameters and no structured output information, it could be more complete by detailing output format or error cases, though it's sufficient for a linter tool.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters3/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is 100%, so the schema fully documents all parameters. The description adds no additional parameter semantics beyond what's in the schema (e.g., it doesn't explain 'top_module' usage or language-specific nuances). Baseline 3 is appropriate as the schema does the heavy lifting.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

The description clearly states the tool's purpose with specific verbs ('lint HDL source code') and resources ('using iverilog or ghdl'), distinguishing it from siblings like format_hdl, simulate, or synthesize. It explicitly mentions the languages supported (Verilog/SystemVerilog/VHDL) and the outcome ('returns warnings and errors').

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines4/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description provides clear context for when to use this tool ('so you can fix them before synthesis'), implying it's a pre-synthesis step. However, it doesn't explicitly state when not to use it or name alternatives among siblings like get_diagnostics or simulate, which might offer overlapping functionality.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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