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simulate

Compile and simulate Verilog designs with testbenches using Icarus Verilog to validate FPGA logic and identify runtime errors through displayed output.

Instructions

Compile and simulate Verilog using Icarus Verilog (iverilog + vvp). Provide the design source and a separate testbench. Returns all $display/$monitor output and any runtime errors.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
codeYesVerilog design source
testbenchYesVerilog testbench source
timeoutNoTimeout in seconds
Behavior3/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations provided, the description carries the full burden. It discloses key behavioral traits: it compiles and simulates, uses specific tools (iverilog + vvp), returns output from $display/$monitor and runtime errors, and implies a timeout via the parameter. However, it lacks details on permissions, rate limits, or error handling beyond runtime errors.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness5/5

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is appropriately sized and front-loaded, with two sentences that efficiently convey purpose, inputs, and outputs without wasted words. Every sentence adds necessary information, making it highly concise and well-structured.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness3/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

Given the tool's complexity (simulation with compilation), no annotations, and no output schema, the description is adequate but has gaps. It covers the basic operation and outputs but lacks details on error types, output format, or prerequisites, which could be important for a simulation tool with multiple parameters.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters3/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is 100%, so the schema already documents all parameters. The description adds marginal value by mentioning 'design source' and 'testbench' which align with 'code' and 'testbench' parameters, but does not provide additional syntax, format details, or usage examples beyond what the schema provides.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

The description clearly states the specific action ('Compile and simulate Verilog') using specific tools ('Icarus Verilog (iverilog + vvp)'), distinguishes from siblings by focusing on simulation rather than formatting, linting, synthesis, or IP management, and explicitly mentions the required inputs ('design source and a separate testbench').

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines4/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description provides clear context for when to use this tool (for Verilog simulation with Icarus Verilog) and implies usage by specifying the required inputs, but does not explicitly state when not to use it or name alternatives among the sibling tools (e.g., 'synthesize' or 'lint_hdl' for other tasks).

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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