simulate
Compile and simulate Verilog designs with testbenches using Icarus Verilog to validate FPGA logic and identify runtime errors through displayed output.
Instructions
Compile and simulate Verilog using Icarus Verilog (iverilog + vvp). Provide the design source and a separate testbench. Returns all $display/$monitor output and any runtime errors.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | Verilog design source | |
| testbench | Yes | Verilog testbench source | |
| timeout | No | Timeout in seconds |