format_hdl
Format Verilog, SystemVerilog, or VHDL source code using industry-standard tools to ensure consistent style and readability in FPGA development workflows.
Instructions
Format HDL source code and return the result. Verilog/SystemVerilog: uses verible-verilog-format. VHDL: uses vsg (pip install vsg). Returns the formatted code and whether it changed.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| code | Yes | HDL source code to format | |
| language | No | HDL language variant | verilog |