Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
| PYTHONPATH | No | The path to the fpgaZeroMCP source directory, used by Python to locate the server modules (registry, tools, etc.) when executing the server script. | |
| USERCORES_PATH | No | A list of additional local HDL directories to scan for cores. Use colon-separated paths on Linux/macOS and semicolon-separated paths on Windows. | |
| FPGAZERO_ALLOWED_LICENSES | No | A comma-separated list of SPDX license IDs allowed when importing cores from GitHub. Default is 'MIT, GPL-2.0, GPL-3.0, LGPL-2.1, LGPL-3.0'. |
Capabilities
Features and capabilities supported by this server
| Capability | Details |
|---|---|
| tools | {
"listChanged": false
} |
| experimental | {} |
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| lint_hdl | Lint HDL source code using iverilog (Verilog/SystemVerilog) or ghdl (VHDL). Returns warnings and errors so you can fix them before synthesis. |
| synthesize | Synthesize Verilog HDL using Yosys or run LiteX backend. Returns resource statistics and the list of inferred modules. Supported targets: generic, ice40, ecp5, gowin, xilinx, intel. |
| place_and_route | Synthesize Verilog with Yosys then place-and-route with nextpnr in one step. If backend=litex, runs LiteX build and ignores Verilog inputs. Returns max frequency, critical path, resource utilization, and full logs. Supported targets: ice40, ecp5, nexus, gowin. Common device/package values: ice40: device=hx1k|hx8k|up5k|lp1k package=tq144|qn84|sg48|cm81 ecp5: device=25k|45k|85k package=CABGA256|CABGA381 nexus: device=LIFCL-40-9BG400C (package embedded in device string) gowin: device=GW1N-UV4LQ144C6/I5 (package embedded in device string) |
| simulate | Compile and simulate Verilog using Icarus Verilog (iverilog + vvp). Provide the design source and a separate testbench. Returns all $display/$monitor output and any runtime errors. |
| list_ip_cores | List all available IP cores in the registry. Optionally filter by category. |
| get_ip_core | Fetch the full manifest and HDL source files for a named IP core. |
| search_github_cores | Search GitHub for open-source MIT-licensed FPGA IP cores. Returns repo names, star counts, descriptions and topics. Use import_github_core to download a result into the local registry. |
| import_github_core | Download an MIT-licensed GitHub repository and add it to the local IP core registry. Automatically uses FuseSoC CAPI2 metadata (.core file) if one exists in the repo. After import, the core is immediately available via get_ip_core and generate_ip. |
| import_fusesoc_core | Import a local FuseSoC CAPI2 .core file into the registry. HDL files referenced in the .core file must exist in the same directory. Useful when you already have FuseSoC cores checked out locally. |
| generate_ip | Generate a parameterized instance of an IP core. Returns the HDL source files and a ready-to-paste Verilog instantiation snippet with the requested parameter values applied. |
| get_diagnostics | Return structured lint diagnostics (line, column, severity, message) for HDL source. Verilog/SystemVerilog: uses Verilator (primary) with verible-verilog-lint as fallback. VHDL: uses GHDL. All tools are part of OSS CAD Suite. |
| format_hdl | Format HDL source code and return the result. Verilog/SystemVerilog: uses verible-verilog-format. VHDL: uses vsg (pip install vsg). Returns the formatted code and whether it changed. |
| litex_build | Run LiteX board target with --build. Returns logs and output directory. |
| litex_soc | Generate LiteX SoC without building gateware. Returns logs and output directory. |
| litex_flow | Run a generic LiteX board target with caller-provided args. |
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
No prompts | |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
No resources | |