pcb_validate_ddr_topology
Validate DDR memory interface topology automatically, checking byte-lane grouping, DQ-DQS skew, inter-byte-lane skew, address/command-to-clock skew, and fly-by routing against JEDEC limits.
Instructions
Auto-detect and validate DDR memory interface topology from classified nets. Checks byte-lane grouping, DQ-DQS skew, inter-byte-lane skew, addr/cmd-to-clock skew, and fly-by topology against JEDEC limits.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| session_id | Yes | Session ID from pcb_parse_layout | |
| ddr_standard | No | DDR standard (default DDR4) |