pcb_analyze_ddr_timing_budget

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations, the description carries the burden of disclosing behavior. It describes the calculation performed (setup/hold margins per DQ bit vs DQS) and the JEDEC reference, providing useful context. However, it does not disclose limitations, assumptions (e.g., ideal transmission line, no crosstalk), or what the output actually looks like (e.g., pass/fail table).

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Is the description appropriately sized, front-loaded, and free of redundancy?

Two sentences, front-loaded with the primary action and scope. Every word adds value, no filler or repetition.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a complex analysis tool with no output schema and no annotations, the description gives a high-level summary of the calculation but lacks sufficient detail for correct invocation. It does not explain the return value structure (e.g., per-lane margins, pass/fail indicators), required vs. optional inputs, or any steps to prepare data. It is adequate for selecting the tool but not fully complete for using it.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema coverage is 75%, so the baseline is 3. The description adds general context linking parameters (byte lanes, DQS/DQ) to the analysis, but does not explain specific parameter semantics beyond the schema. It does not compensate fully for the undocumented ddr_standard parameter or provide details on how inputs like trace lengths are used.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Does the description clearly state what the tool does and how it differs from similar tools?

The description uses a specific verb ('analyze') with a clear resource ('DDR timing margin') and detailed scope ('per-lane', 'against JEDEC budget', 'setup/hold margins for each DQ bit relative to DQS'). This clearly distinguishes it from sibling tools like pcb_analyze_ddr or pcb_analyze_timing by emphasizing the per-lane budget calculation.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Does the description explain when to use this tool, when not to, or what alternatives exist?

No explicit guidance on when to use this tool versus alternatives. The description implies it is for detailed margin analysis, but does not state scenarios or exclusions, such as 'use for final DDR compliance checks' or 'not for topology validation.' No mention of alternative tools.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.