pcb_analyze_signal_flow
Analyze clock, reset, and JTAG/SWD signal flow in PCB schematics to detect clock fan-out, reset contention, missing debug headers, and absent supervisor ICs.
Instructions
Trace clock distribution, reset distribution, and JTAG/SWD accessibility through the schematic. Flags clock fan-out > 4 unbuffered loads, multi-driver reset contention, ICs without debug headers, and reset nets missing a supervisor IC.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| session_id | Yes | Session id with schematic data. |