Parse a PCB layout file (KiCad, ODB++, Gerber, Altium, IPC-2581). Returns session_id for subsequent queries. If a session_id from pcb_start_professional_review is supplied, parsed data is written into that existing session (preserves playbook state).

Get layer stackup from a parsed design.

Get component list from a parsed design.

Get net list from a parsed design.

Get via list from a parsed design.

Get trace summary from a parsed design.

Get drill table: sizes, counts, plating types, aspect ratios.

Get board outline: dimensions, area, vertices, cutouts.

Get extracted DRC constraints: min trace, min space, min drill, min annular ring.

Get copper pour/zone data: areas, nets, clearances per layer.

Get fab notes, material specs, and manufacturing info.

Calculate microstrip trace impedance using IPC-2141 formulas.

Calculate stripline (buried trace between ground planes) impedance.

Calculate differential pair impedance for USB, HDMI, Ethernet, etc.

Calculate minimum trace width for current capacity (IPC-2221).

Calculate coplanar waveguide (CPW/GCPW) impedance using conformal mapping. Supports grounded and ungrounded CPW.

Calculate skin depth, AC resistance factor, and conductor loss including Hammerstad surface roughness correction.

Calculate dielectric loss (dB/inch, total dB) for a trace at frequency. Accounts for material loss tangent.

Calculate power/ground plane cavity resonance frequencies. Identifies modes that can amplify noise and cause EMI.

Calculate required via stitching density and spacing for EMI containment at a given frequency. Uses lambda/20 rule.

Detailed power/ground plane cavity resonance analysis. Calculates all TM modes, Q factors, peak impedances, identifies problematic modes near common clocks, and provides decoupling cap recommendations.

Calculate frequency-swept insertion loss (S21) and return loss (S11) for a PCB trace. Models conductor loss (skin effect + Hammerstad roughness), dielectric loss, and mismatch loss.

Calculate return loss (S11), mismatch loss, and VSWR from impedance mismatch.

Analyze differential pair mode conversion: even/odd mode impedances, SCD21 from length asymmetry, common-mode current estimate, and EMI impact.

Analyze timing margins for high-speed signals.

Analyze crosstalk between parallel traces (NEXT and FEXT).

Analyze via electrical characteristics.

Analyze differential pair routing quality.

Analyze trace length matching for a group of signals.

Calculate statistical eye diagram for a high-speed serial channel. Models lossy transmission line (conductor + dielectric loss) and estimates eye opening, jitter, and pass/fail vs standard thresholds.

Estimate radiated emissions from a current loop for EMC.

Estimate signal bandwidth and EMC concerns from rise time.

Analyze shielding effectiveness of an enclosure.

Analyze ESD protection for a circuit.

Analyze grounding topology.

Predict EMC compliance for given design parameters.

Estimate return current density distribution on a reference plane beneath a signal trace. Shows how current concentrates under the trace at high frequencies and spreads at low frequencies. Identifies crowding near plane gaps/edges.

Optimize ground via stitching pattern for a reference plane. Calculates spacing from lambda/20 rule and suggests via locations accounting for existing vias and plane gaps.

Analyze DDR memory interface routing.

Analyze PCIe lane routing.

Calculate PCIe link insertion loss budget and equalizer margin. Sums trace, connector, via, and package losses then compares against the PCIe generation spec limit.

Validate PCIe lane-to-lane skew against generation-specific spec limits. Calculates per-lane propagation delay and max skew.

Analyze USB routing.

Analyze Ethernet PHY routing.

Auto-detect and validate DDR memory interface topology from classified nets. Checks byte-lane grouping, DQ-DQS skew, inter-byte-lane skew, addr/cmd-to-clock skew, and fly-by topology against JEDEC limits.

Detailed per-lane DDR timing margin analysis against JEDEC budget. Calculates setup/hold margins for each DQ bit relative to DQS.

Analyze power distribution network impedance.

Frequency-swept PDN impedance profiling. Models VRM, bulk caps, MLCC decaps, and plane capacitance as parallel RLC networks. Sweeps from freq_start to freq_stop and flags anti-resonance peaks exceeding the target impedance Z_target = V * ripple% / I_max.

Analyze decoupling capacitor placement.

Analyze VRM placement and routing.

Analyze solder paste stencil design.

Analyze component placement for manufacturability.

Analyze board assembly process considerations.

Analyze manufacturing tolerance stackup.

Analyze thermal dissipation for a component.

Analyze thermal via array for heat dissipation.

Analyze copper area heat spreading.

Check if a trace could act as unintentional antenna.

Analyze slot in ground plane as unintentional antenna.

Analyze common-mode noise on differential pairs.

Analyze cable-to-cable coupling for EMI.

Trace ground return current path for a specific net. Shows return path segments, loop area, split crossings, and via transition quality.

Analyze return paths for all high-speed signal nets. Identifies split-plane crossings, inadequate return vias, and calculates effective loop areas.

Find signals crossing ground plane splits/slots. Each crossing forces return current to detour, increasing loop area and EMI risk.

Score EMI risk per net and identify top concerns. Combines return path quality, loop area, frequency content, and current to predict emissions.

Predict radiated emission spectrum vs regulatory limits. Calculates emission level at each harmonic and compares to FCC/CISPR limits.

Identify board regions with highest EMI risk. Clusters high-risk nets by location and returns spatial hot-spots.

Classify all nets by function (power, ground, DDR, USB, PCIe, etc.) with confidence scores. Detects differential pairs automatically.

Detect high-speed interfaces (DDR, PCIe, USB, Ethernet, LVDS, RF) with pin counts and associated nets.

Classify overall design type (rf, mixed_signal, high_speed_digital, power, simple_digital) with complexity score (1-10).

Get common PCB stackup templates with typical impedances.

Get dielectric properties for common PCB materials.

Parse a STEP (.step/.stp) file for 3D mechanical review. Extracts board outline, component bounding boxes, heights. Returns session_id.

Get component-to-component and component-to-board-edge 3D clearances from STEP data.

Check if PCB assembly fits within an enclosure with required clearances.

Render SVG board view with component placement, traces, vias. Supports layer filtering, net/component highlighting.

Render SVG cross-section of the PCB layer stackup showing copper, dielectric, solder mask layers with thicknesses.

Render SVG highlighting a specific net's traces and vias on the board.

Render SVG board view with annotation overlays (arrows, text callouts, highlight regions, warning markers).

Export an SVG render (board, stackup, net, annotated) to a PNG image file. Requires cairosvg.

Generate and export all standard renders (board, stackup, key nets, annotated findings) as PNG files to a directory. Returns mapping of label to file path.

Generate a professional DOCX design review report with embedded board renders, schematic images, and analysis findings. Requires python-docx and cairosvg.

Parse a PDF schematic to extract component references, net labels, and page data. Uses text-layer extraction (requires pymupdf for full support). If session_id provided, attaches schematic data to existing layout session for cross-reference.

Get extracted text and annotations for a specific schematic PDF page. Returns page text, detected components, and net labels. If pymupdf is installed, can also render the page as an image.

Cross-reference schematic components/nets against layout. Finds missing components, extra components, value mismatches, and unrouted nets. Requires both schematic and layout data in the session.

Parse a schematic file with auto format detection (.kicad_sch, .SchDoc, .pdf, .net). Populates schematic_components and schematic_nets on the session. Use over pcb_parse_schematic_pdf when you want format-agnostic parsing.

Parse a BOM (CSV or Excel) and attach the items to the session for downstream cross-reference and rating analyzers.

Walk the schematic's power nets and report missing bulk/bypass caps, ungrounded rails, and rails without an identified regulator/input source. Requires schematic data via pcb_parse_schematic.

Identify external-facing nets (USB, Ethernet, antenna ports, GPIO headers, CAN/LIN buses, etc.) and check for TVS/ESD diodes, common-mode chokes on differential pairs, and fuses on power inputs.

For each IC in the schematic, count capacitors on its Vdd-class nets and flag ICs under-decoupled relative to the 1-cap-per-Vdd-pin guideline.

Trace clock distribution, reset distribution, and JTAG/SWD accessibility through the schematic. Flags clock fan-out > 4 unbuffered loads, multi-driver reset contention, ICs without debug headers, and reset nets missing a supervisor IC.

Compare schematic, BOM, and layout component lists in one pass. Detects missing components, footprint mismatches, value mismatches, DNP flag inconsistencies, MPN divergence, and manufacturer differences. Severity-graded per the playbook.

ENTRY POINT for a meticulous senior-consulting-engineer design review. Call this FIRST, before any parser or analyzer. Classifies the user's input files (schematic, layout, stackup, BOM, STEP, etc.), selects the per-market question pack and standards shortlist, and returns the binding 8-pass playbook (P0-P8) that Claude must follow. See docs/CLAUDE_REVIEW_PLAYBOOK.md.

Set or add a market on an existing review session (e.g. switching from commercial to automotive, or adding wireless on top of medical for a connected device). Updates the session's question pack and standards shortlist. Call before pcb_get_review_questions to receive the merged pack.

Return the per-standard coverage report for the session: which analyzers ran, which are still required, which standards are stub or unimplemented. Surfaces gaps the human reviewer should resolve before final sign-off.

Run the preflight gate. Refuses to advance unless the active markets' required questions are answered, at least one standard is selected, and no stub/unimplemented standards lack a human-review note. Returns a ValidationGate breakdown.

Set design review context: requirements, standards, known issues, operating conditions. Call before pcb_run_design_review.

Get list of questions the tool needs answered for a complete design review. Call after parsing, before running review. Returns questions tailored to the detected interfaces and design characteristics.

Provide answers to review questions identified by pcb_get_review_questions. Call before running design review to supply missing context.

Run full automated multi-domain design review. Classifies design, selects relevant analyzers, runs analysis, cross-correlates findings, and generates structured results.