pcb_analyze_timing
Analyze setup and hold timing margins for high-speed signal traces using trace length, data rate, and rise time to flag violation risks.
Instructions
Analyze timing margins for high-speed signals.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| effective_er | Yes | ||
| hold_time_ps | Yes | ||
| rise_time_ps | Yes | ||
| setup_time_ps | Yes | ||
| data_rate_gbps | Yes | ||
| trace_length_mm | Yes |