rp_build_project
Builds a RedPitaya PS+PL Vivado project end-to-end: runs setup TCL, synthesis, implementation, write_bitstream, and generates the .bit.bin; returns stage, paths, and timing.
Instructions
Build a RedPitaya PS+PL project end-to-end: run the repo's project setup TCL (creates the PS7 block design from ip/system.tcl), then synthesis, implementation and write_bitstream, then generate the .bit.bin. Returns {stage, xpr_path, bit_path, bin_path, timing}. Requires start_session first.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| jobs | No | Parallel jobs for synth/impl (default: 4) | |
| model | No | Board model — only 'Z10' supported (default: Z10) | |
| defines | No | Extra Verilog defines passed as tclarg 1 (default: empty) | |
| project | Yes | Project under prj/ to build (e.g. 'v0.94', 'barebones') | |
| synth_flags | No | Extra synth_design flags via STEPS.SYNTH_DESIGN.ARGS.MORE_OPTIONS. Default empty. RedPitaya canonical for reproducibility: '-flatten_hierarchy none -bufg 16 -keep_equivalent_registers' (NOTE: those preserve hierarchy/BUFG count for debug; on xc7z010-1 they typically hurt QoR vs defaults). | |
| impl_timeout | No | Implementation timeout s (default: 5400) | |
| setup_timeout | No | Project-setup TCL timeout s (default: 900) | |
| synth_timeout | No | Synthesis timeout s (default: 2400) | |
| workspace_path | Yes |