create_redpitaya_project_rtl
Build a Red Pitaya RTL Vivado project from Verilog sources and XDC constraints, then run synthesis, implementation, and bitstream generation, stopping at the first failing stage.
Instructions
One-shot composite: create project -> add HDL sources -> apply XDC -> synth -> impl -> write_bitstream -> generate .bit.bin. Stops on the first failing stage and returns a structured payload.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| jobs | No | ||
| name | Yes | ||
| board | No | default: red_pitaya_125_14 | |
| directory | Yes | ||
| top_module | Yes | ||
| synth_flags | No | ||
| xdc_variant | No | ||
| impl_timeout | No | ||
| synth_timeout | No | ||
| verilog_files | Yes | ||
| extra_xdc_files | No |