add_sources
Add Verilog, SystemVerilog, or VHDL files to a Vivado project, optionally set the top module, and update compile order for correct builds.
Instructions
Add HDL source files (.v/.sv/.vhd) to the current project. Optionally sets the top module and updates compile order.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| files | Yes | Absolute paths to HDL source files | |
| fileset | No | Target fileset (default: sources_1) | |
| set_top | No | If given, set this module as project top after adding files |