Start a persistent Vivado TCL session. Must be called before project/design tools. Vivado startup is ~30s; the session is reused across tool calls.

Stop the Vivado TCL session and free resources.

Get statistics for the current Vivado session (commands run, timing, errors).

Verify the Vivado process is responsive. With auto_recover=true the session is restarted if it hangs.

Get host hostname, free memory, and session state. Useful to check there is enough RAM before launching synthesis/implementation.

Open an existing Vivado project (.xpr file).

Close the currently open project.

Get name, part, target language, directory of the open project.

Create a new Vivado project on disk in project mode. Defaults to the Red Pitaya STEMlab 125-14 part (xc7z010clg400-1). Call add_sources / add_constraints next, then run_synthesis.

Add HDL source files (.v/.sv/.vhd) to the current project. Optionally sets the top module and updates compile order.

Add XDC constraint files to the current project.

List boards with bundled XDC + metadata. No Vivado session required.

Get bundled metadata for a board: part, LED pinout, absolute XDC paths, default synth flags. Use the returned absolute_path values with add_constraints. No Vivado session required.

Run synthesis on the current project (reset_run -> launch_runs synth_1 -> wait_on_run). Returns ground-truth status from the run object, not just text parsing.

Run implementation (opt_design -> place_design -> route_design). Returns ground-truth status from the impl_1 run object.

Generate bitstream — launch_runs impl_1 -to_step write_bitstream -> wait_on_run. Returns ground-truth run status and the .bit path.

Set the strategy of a synthesis or implementation run (e.g. synth_1 'Flow_PerfOptimized_high', impl_1 'Performance_NetDelay_high'). On an unknown name, Vivado's error lists the valid strategies.

Get timing summary (WNS, TNS, WHS, THS). Returns parsed metrics by default. Use generate_full_report for raw output.

Get failing/critical timing paths. Returns structured summary by default; use detail_level=standard|full for the raw text too.

Resource utilization (LUT/FF/BRAM/DSP/IO). Parsed only by default.

Get clock information and constraints (report_clocks).

Get Vivado messages filtered by severity (error/critical/warning/all).

Get the design hierarchy (modules and instances), optionally filtered.

Get top-level I/O ports of the design.

Search for nets by pattern (default '*').

Search for cells/instances by pattern.

Launch xsim in behavioral/post-synth/post-impl mode.

Run the simulation for a specified time (e.g. 100ns, 1us, all).

Restart the simulation from time 0.

Close the current simulation.

Get the current simulation time (current_time).

Get current value of a signal in simulation.

Get values of multiple signals matching a wildcard pattern (max 50).

Add signals to the waveform viewer.

Set the top-level testbench module for simulation.

List simulation objects in a scope (signals/ports/internal).

List child scopes (hierarchy) in the simulation.

Step simulation by delta cycles.

Add a breakpoint on signal edge or change.

Remove all breakpoints (remove_bps -all).

Get simulation log messages filtered by severity.

Execute a raw TCL command in Vivado. Use for advanced ops not covered by other tools.

Source a .tcl script file in the Vivado session (uses source under the hood). Helpful for replaying canonical Red Pitaya / Xilinx reference scripts.

Create a new block design and make it current. Optionally sets the board_part property on the project beforehand (board_part requires the BSP to be installed in Vivado).

Save the currently open block design to disk.

Close the currently open block design (without deleting).

List cells in the current block design (optionally filtered).

Add an IP core to the current block design (create_bd_cell -type ip -vlnv ...). If config is provided, the CONFIG.* keys are applied via set_property -dict.

Create a top-level port on the current block design. Scalar or vector (from/to) via create_bd_port, or an interface port when vlnv is given (create_bd_intf_port, e.g. the XADC 'xilinx.com:interface:diff_analog_io_rtl:1.0'). Port names must match the constraints (XDC) of the board.

Add an RTL module (Verilog/VHDL already in the project, see add_sources) to the current block design as a module-reference cell (create_bd_cell -type module -reference). Optional config sets its parameters, e.g. {'CONFIG.WIDTH': '8'}; string parameters keep their quotes, e.g. {'CONFIG.init': '"0011"'}.

Set CONFIG.* properties on an existing block-design cell (set_property -dict). Use for settings that must be applied after creation or in a separate step, e.g. importing a PS7 board preset: {'CONFIG.PCW_IMPORT_BOARD_PRESET': '/red_pitaya.xml'}.

Connect two scalar pins/ports in the current block design.

Connect two AXI/interface pins in the current block design.

Use apply_bd_automation -rule xilinx.com:bd_rule:axi4 to wire an AXI master to a slave (inserts AXI interconnect + clock/reset hookups).

Apply the Zynq-7000 processing_system7 board preset to a PS7 cell — wires FIXED_IO / DDR / clocks per the board definition. Equivalent to clicking 'Run Block Automation' on a freshly added PS7 in the GUI.

Run validate_bd_design and return parsed status. Failures include unconnected pins, conflicting CONFIG values, or missing assignments.

Regenerate the block design layout (cosmetic; useful before save).

Auto-assign addresses in the BD address editor (assign_bd_address).

Generate the HDL wrapper for a block design and (by default) add it to sources_1 and set it as project top. Implements the canonical pattern: make_wrapper -files -top; add_files -norecurse ; set_property top [current_fileset]; update_compile_order.

Create an IP from the Xilinx IP catalog. Generates a .xci file in the project's IP sources fileset. Use configure_ip + generate_ip_target afterwards, then run synth_ip if you want out-of-context synthesis.

Set CONFIG.* properties on an existing IP via set_property -dict.

Generate IP output products (synthesis + simulation by default).

Run out-of-context (OOC) synthesis on an IP.

Upgrade IP version (no-op if already at latest).

Get a structured snapshot of the project's IP and their upgrade status.

Open the Hardware Manager (no JTAG connection yet).

Close the Hardware Manager.

Connect to a hw_server (cs_server). Default URL is localhost:3121 — the value Vivado uses when running hw_server locally.

Refresh the currently selected hardware device (re-reads JTAG chain state). Call after re-plugging a cable.

Program a .bit onto the first device on the JTAG chain. Sequence: open_hw_target -> set PROGRAM.FILE -> program_hw_devices. The hardware must already be connected (open_hw_manager + connect_hw_server).

Run report_power and return parsed totals (total/dynamic/static W) + a truncated raw block. Full output stored at /tmp/vivado_red_mcp/.

Run report_drc and return parsed violations list (severity/code/message). Use after place_design/route_design to catch design-rule problems.

Run report_methodology (UltraFast methodology checks). Returns violation list grouped by severity.

Run report_qor_assessment (overall design quality score).

Run report_clock_interaction to find cross-clock paths (timed/async/unconstrained).

Resolve a bundled board XDC and attach it to the current project. Standalone wrapper over get_board_info + add_constraints.

Convert a .bit into a raw binary image (.bit.bin) loadable via /dev/xdevcfg on the Red Pitaya. Use after generate_bitstream.

Return structured errors and critical warnings from a run's log (default: synth_1), plus those of every failed run (e.g. out-of-context IP runs). Use after run_synthesis fails to get a clean actionable list.

One-shot composite: create project -> add HDL sources -> apply XDC -> synth -> impl -> write_bitstream -> generate .bit.bin. Stops on the first failing stage and returns a structured payload.

Download the RedPitaya-FPGA repo from GitHub as a source zip and extract it (no git required, stdlib only). Returns repo_path to feed into rp_setup_workspace. Idempotent — pass force=true to redownload. No Vivado session required.

Copy a RedPitaya-FPGA repo into an isolated workspace so builds don't touch the pristine checkout. The copy is patched to run on the installed Vivado release (block-design version check) and without git. Idempotent — pass force=true to recopy. No Vivado session required.

List projects under prj/ of a RedPitaya workspace or repo. Flags which are Z10-capable (have ip/system.tcl or legacy ip/systemZ10.tcl). No Vivado session required.

Report workspace state: projects present and which already have a built bitstream.

Clone an existing prj/ into prj/ inside the workspace, ready for custom PL logic. Returns the rtl/ dir and red_pitaya_top path to edit. No Vivado session required.

Build a RedPitaya PS+PL project end-to-end: run the repo's project setup TCL (creates the PS7 block design from ip/system.tcl), then synthesis, implementation and write_bitstream, then generate the .bit.bin. Returns {stage, xpr_path, bit_path, bin_path, timing}. Requires start_session first.

Copy a .bit.bin to a Red Pitaya over SSH/SCP and load it into the FPGA. Uses /dev/xdevcfg (works on Red Pitaya OS 1.04 + 2.00) or fpgautil (OS 2.00). No Vivado session required.

Run an arbitrary shell command on a Red Pitaya over SSH and return stdout/stderr/exit code. Useful for status checks, dmesg reads, manual loader invocations.

Look up a topical Vivado documentation summary bundled with this server. Returns markdown content + upstream URL. Known topics: block_design, ps7_zynq, timing_constraints, synthesis_strategies, simulation_xsim, red_pitaya_125_14, redpitaya_ps_pl_flow, tcl_quoting, hw_manager, ip_integrator, pitfalls_2020_1.

List the bundled Vivado documentation topics.

Submit a feature request for the Vivado MCP server (persisted on disk).

List all submitted feature requests.

Generate a full Vivado report to a file. Use when inline reports get truncated or you need the complete output. Returns a report_id usable with read_report_section.

Read a section of a previously generated report. Provide report_id (from generate_full_report) or a direct file_path.