create_project
Create a Vivado project on disk in project mode, defaulting to the Red Pitaya STEMlab 125-14 part, then add sources and constraints before synthesis.
Instructions
Create a new Vivado project on disk in project mode. Defaults to the Red Pitaya STEMlab 125-14 part (xc7z010clg400-1). Call add_sources / add_constraints next, then run_synthesis.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| name | Yes | Project name | |
| part | No | Xilinx part number (default: xc7z010clg400-1) | |
| force | No | Overwrite existing project (default: true) | |
| directory | Yes | Parent directory; project created at <directory>/<name> | |
| target_language | No | Verilog or VHDL (default: Verilog) |