load_vhdl
Load VHDL source files into the active session for elaboration and design structure queries. Load dependency files first, then the top file.
Instructions
Load VHDL into the active session (beta, restricted two-state RTL subset). Load dependency/package files first, one call per file, then the top file. Package-only files or entities awaiting generics may return top=null. Use hierarchy, cards and connectivity queries on the elaborated design. SystemVerilog intent recovery is unavailable; source ranges are not guaranteed. Unsupported constructs may fail during beta development. Returns the top summary when elaborated, language and beta status.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| top | No | Top entity name; omit to infer the top. | |
| file | Yes | One local VHDL source file path (.vhd or .vhdl). |