load_verilog

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

Annotations only establish that this is a non-read-only, non-destructive, closed-world, non-idempotent operation. The description adds real context beyond that: ordering dependencies on other loaders, the failure mode for unresolved modules, and a downstream consequence (get_source/get_intent cannot answer for gate netlists).

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Is the description appropriately sized, front-loaded, and free of redundancy?

Four tight sentences, front-loaded with the core action, then prerequisites, alternatives, and limitations. Every sentence carries distinct information with no filler.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

No output schema exists, yet the description covers prerequisites, alternatives, failure behavior, and the downstream limitations of the loaded artifact. Nothing an agent needs in order to call this correctly is missing.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is 100%, so the schema already documents all three parameters including allow_unknown_designs and keep_assigns. The description echoes allow_unknown_designs' effect but adds no syntax, format, or default guidance beyond the schema, so the baseline of 3 applies.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Does the description clearly state what the tool does and how it differs from similar tools?

States a specific verb (Load) and resource (local gate-level/structural Verilog into the active session) and explicitly distinguishes itself from load_systemverilog for RTL elaboration. An agent can separate it from load_vhdl, load_liberty, and load_primitives without opening any schema.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Does the description explain when to use this tool, when not to, or what alternatives exist?

Gives explicit preconditions (call load_liberty for Liberty cells or load_primitives for built-ins first), a named alternative with its selecting condition (load_systemverilog for RTL), and a failure condition (unknown modules fail unless allow_unknown_designs is true). Nothing is left to inference.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.