load_verilog
Load gate-level Verilog netlists for structural analysis. Use with liberty or primitives to resolve cells; blackboxes unknown modules when allow_unknown_designs is set.
Instructions
Load gate-level/structural Verilog netlists. Pair with load_liberty (or load_primitives) so cells resolve to real models; allow_unknown_designs=True blackboxes any module still undefined instead of failing. Gate netlists carry no source info, so get_source/get_intent cannot answer for them.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| files | Yes | ||
| keep_assigns | No | ||
| allow_unknown_designs | No |