load_systemverilog
Elaborate SystemVerilog designs from files or flist, producing a netlist for structural queries across hierarchy and connectivity.
Instructions
Elaborate SystemVerilog (files and/or an flist; optional top module). Anonymous lowered objects are addressable by #. intent=True retains naja's in-engine SNL↔slang link for get_intent.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| top | No | ||
| files | No | ||
| flist | No | ||
| intent | No | ||
| keep_assigns | No |